Gate metal recess for oxidation protection and parasitic capacitance reduction
View Patent ↗A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.
1. A method of fabricating a semiconductor device, the semiconductor device including a gate stack structure having at least one gate stack sidewall, the gate stack structure including one or more metal layers forming a gate metal, said method comprising:
recessing the gate metal away from the gate stack sidewall using a chemical etch; and
selectively oxidizing only the gate metal of the gate stack structure to form a gate metal oxide that at least partly fills the recess.
2. The method of claim 1 , wherein the chemical etch is carried out using a gaseous etching solution.
3. The method of claim 1 , wherein the chemical etch is carried out using a wet etching solution.
4. The method of claim 1 , further comprising forming a gate spacer on the gate stack sidewall.
5. The method of claim 1 , wherein the gate metal is disposed above a gate oxide.
6. The method of claim 1 , wherein the gate metal includes at least one of W and WSi x .
7. A method of fabricating a semiconductor device, the semiconductor device including a gate stack structure having at least one gate stack sidewall, the gate stack structure including one or more metal layers forming a gate metal, said method comprising:
recessing the gate metal away from the gate stack sidewall using a chemical etch;
selectively oxidizing only the gate metal of the gate stack structure to form a gate metal oxide that at least partly fills the recess; and
forming a gate spacer on the gate stack sidewall.