IP Library Assignment 037221/0885
Patent Assignment
Reel/Frame 037221/0885

Assignment of Assignor's Interest

Recorded: 2015-12-07 Pages: 8
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-09-30
Assignee
SAMSUNG ELECTRONICS CO., LTD.
129, SAMSUNG-RO, YEONGTONG-GU, GYEONGGI-DO, SUWON-SI, 443-742, KOREA, REPUBLIC OF
Covered Properties (56)
Etching High Aspect Contact Holes in Solid State Devices
Patent: 6,008,121 →
Application: 08/618,161 →
Crack Stop Formation for High-Productivity Processes
Patent: 5,776,826 →
Application: 08/642,983 →
Pad Stack with a Poly Si Etch Stop for Teos Mask Removal with Rie
Patent: 5,776,808 →
Application: 08/777,156 →
Crack Stops
Patent: 5,789,302 →
Application: 08/823,668 →
Dummy Patterns for Aluminum Chemical Polishing (Cmp)
Patent: 6,093,631 →
Application: 09/007,911 →
Reduced Voltage Input/Reduced Voltage Output Tri-State Buffers
Patent: 6,181,165 →
Application: 09/037,289 →
Device Interconnection
Patent: 6,870,263 →
Application: 09/052,688 →
Crack Stops
Patent: 6,025,639 →
Application: 09/061,538 →
Removal of Post-Rie Polymer on A1/Cu Metal Line
Patent: 5,980,770 →
Application: 09/061,565 →
Geometrical Control of Device Corner Threshold
Patent: 5,998,852 →
Application: 09/078,517 →
Semiconductor Structure Including a Conductive Fuse and Process for Fabrication Thereof
Patent: 6,037,648 →
Application: 09/105,647 →
Geometrical Control of Device Corner Threshold
Patent: 6,022,796 →
Application: 09/120,190 →
A Method of Manufacturing Semiconductor Structures Including a Pair of Mosfets
Patent: 6,096,664 →
Application: 09/130,324 →
Electrical Fuses with Tight Pitches and Method of Fabrication in Semiconductors
Patent: 6,008,523 →
Application: 09/140,573 →
Removal of Post-Rie Polymer on A1/Cu Metal Line
Patent: 6,849,153 →
Application: 09/204,706 →
Publication: US 2001/0006166
A Repairable Semiconductor Memory Circuit Having Parallel Redundancy Replacement Wherein Redundancy Elements Replace Failed Elements
Patent: 6,052,318 →
Application: 09/218,561 →
Crack Stops
Patent: 6,271,578 →
Application: 09/218,882 →
Driver Circuit with Negative Lower Power Rail
Patent: 6,127,878 →
Application: 09/225,664 →
Crack Stops
Patent: 6,084,287 →
Application: 09/241,741 →
Dynamic Logic Circuit
Patent: 6,262,615 →
Application: 09/257,304 →
Current Source
Patent: 6,087,820 →
Application: 09/265,252 →
Capacitive Coupled Driver Circuit
Patent: 6,215,349 →
Application: 09/265,253 →
Hierarchical Prefetch for Semiconductor Memories
Patent: 6,081,479 →
Application: 09/333,539 →
Synchronized Data Capturing Circuits Using Reduced Voltage Levels and Methods Therefor
Patent: 6,668,031 →
Application: 09/377,588 →
Semiconductor Structures and Manufacturing Methods
Patent: 6,740,555 →
Application: 09/408,248 →
Prefetch Architectures for Data and Time Signals in an Integrated Circuit and Methods Therefor
Patent: 6,529,054 →
Application: 09/425,329 →
Optimized Decoupling Capacitor Using Lithographic Dummy Filler
Patent: 6,232,154 →
Application: 09/442,890 →
High Performance Cmos Word-Line Driver
Patent: 6,236,617 →
Application: 09/458,878 →
Receiver with switched current feedback for controlled hysteresis
Patent: 6,275,082 →
Application: 09/519,104 →
Cbr refresh control for the redundancy array
Patent: 6,195,300 →
Application: 09/536,185 →
Optimized decoupling capacitor using lithographic dummy filler
Patent: 6,353,248 →
Application: 09/562,220 →
Orientation independent oxidation of silicon
Patent: 6,358,867 →
Application: 09/596,097 →
Power Controlled Input Receiver
Patent: 6,462,613 →
Application: 09/597,121 →
Design Layout for a Dense Memory Cell Structure
Patent: 6,396,096 →
Application: 09/597,401 →
Semiconductor Structures and Manufacturing Methods
Patent: 6,605,860 →
Application: 09/597,442 →
Semiconductor Structure and Method of Fabrication Including Forming Aluminum Columns
Patent: 6,635,564 →
Application: 09/662,424 →
Buffers with Reduced Voltage Input/Output Signals
Patent: 6,426,658 →
Application: 09/676,864 →
Method for Eliminating Crack Damage Induced by Delaminating Gate Conductor Interfaces in Integrated Circuits
Patent: 6,492,247 →
Application: 09/717,970 →
Multi-Level Fuse Structure
Patent: 6,495,901 →
Application: 09/772,377 →
Publication: US 2002/0100956
Method for Low Temperature Chemical Vapor Deposition of Low-K Films Using Selected Cyclosiloxane and Ozone Gases for Semiconductor Applications
Patent: 6,531,412 →
Application: 09/928,209 →
Publication: US 2003/0032306
Unit-Architecture with Implemented Limited Bank-Column-Select Repairability
Patent: 6,680,857 →
Application: 09/964,208 →
Publication: US 2003/0058028
Gate Processing Method with Reduced Gate Oxide Corner and Edge Thinning
Patent: 6,656,798 →
Application: 09/965,919 →
Publication: US 2003/0067035
Process for Forming a Damascene Structure
Patent: 6,649,531 →
Application: 09/994,340 →
Publication: US 2003/0100190
Twisted Bit-Line Compensation for Dram Having Redundancy
Patent: 6,570,794 →
Application: 10/034,626 →
Rtcvd Process and Reactor for Improved Conformality and Step-Coverage
Patent: 6,576,565 →
Application: 10/075,152 →
Repeater with Reduced Power Consumption
Patent: 6,690,198 →
Application: 10/114,195 →
Publication: US 2003/0184342
Method to Enhance Epi-Regrowth in Amorphous Poly Cb Contacts
Patent: 6,740,568 →
Application: 10/206,875 →
Publication: US 2004/0018680
Reduced Hot Carrier Induced Parasitic Sidewall Device Activation in Isolated Buried Channel Devices by Conductive Buried Channel Depth Optimization
Patent: 6,867,472 →
Application: 10/338,517 →
Publication: US 2004/0142500
Adhesion Layer for Pt on SIO2
Patent: 7,270,884 →
Application: 10/408,339 →
Publication: US 2004/0197576
Methods and Apparatus for Providing an Antifuse Function
Patent: 6,882,027 →
Application: 10/447,018 →
Publication: US 2004/0238919
Method for Improved Alignment of Magnetic Tunnel Junction Elements
Patent: 6,933,204 →
Application: 10/605,604 →
Publication: US 2005/0079683
Phase Change Memory Cell Having a Sidewall Contact
Patent: 7,541,609 →
Application: 11/601,304 →
Publication: US 2008/0116442
Phase Change Memory Cell Design with Adjusted Seam Location
Patent: 7,525,176 →
Application: 11/668,992 →
Publication: US 2008/0179591
Integrated Circuit Including Silicide Region to Inhibit Parasitic Currents
Patent: 7,863,610 →
Application: 11/843,044 →
Publication: US 2009/0052230
Concentric Phase Change Memory Element
Patent: 8,124,950 →
Application: 12/198,383 →
Publication: US 2010/0054029
Concentric Phase Change Memory Element
Patent: 9,111,609 →
Application: 13/364,727 →
Publication: US 2012/0134204
Related Assignments (8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023788/0535 →
Assignment of Assignor's Interest Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0401 →
Assignment of Assignor's Interest Jan 14, 2010
From: INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION
To: QIMONDA AG
Reel/Frame 023791/0001 →
Assignment of Assignor's Interest Feb 22, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023963/0502 →
Assignment of Assignor's Interest May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Release of Security Interest May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →