Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by conductive buried channel depth optimization
View Patent ↗A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a surface of the substrate to a first depth. A buried conductive channel layer is formed within the transistor junction between the surface of the substrate and the first depth. The buried conductive channel layer has a peak conduction depth, which is different from a depth of the area susceptible to hot carrier effects.
1. A semiconductor device, comprising:
a transistor junction formed in a substrate adjacent to an isolation region, a region between the transistor junction and the isolation region including an area susceptible to hot carrier effects, the transistor junction extending from a surface of the substrate to a first depth; and
a buried conductive channel layer formed within the transistor junction between the surface of the substrate and the first depth, the buried conductive channel layer having a peak conduction depth which is different than a depth of the area susceptible to hot carrier effects, wherein the peak conduction depth is below the depth of the area susceptible to hot carrier effects.
2. The semiconductor device as recited in claim 1 , wherein the isolation region includes a shallow trench isolation region.
3. The semiconductor device as recited in claim 2 , wherein the shallow trench isolation region includes a nitride liner and the area susceptible to hot carrier effects includes an area between the nitride liner and the transistor junction.
4. The semiconductor device as recited in claim 1 , wherein the buried conductive channel layer includes at least one of boron and boron difluoride dopants.
5. The semiconductor device as recited in claim 1 , wherein the buried conductive channel layer includes arsenic dopants.
6. A semiconductor device, comprising:
a transistor device formed in a substrate adjacent to an isolation region, the transistor device comprising a junction region activated by a gate conductor to conduct charge through the junction region, the junction region extending from a surface of the substrate to a first depth;
a region disposed between the junction region and the isolation region including an area susceptible to charge trapping; and
a charge injection region formed in the junction to provide a peak charge transfer layer through the junction region, the charge injection region having a peak conduction depth which is different than a depth of the area susceptible to charge trapping, wherein the peak conduction depth is below the depth of the area susceptible to charge trapping.
7. The semiconductor device as recited in claim 6 , wherein the isolation region includes a shallow trench isolation region.
8. The semiconductor device as recited in claim 7 , wherein the shallow trench isolation region includes a nitride liner and the area susceptible to charge trapping includes an area between the nitride liner and the junction region.
9. The semiconductor device as recited in claim 6 , wherein the charge injection region includes a buried conductive channel layer.
10. The semiconductor device as recited in claim 6 , wherein the charge injection region includes dopants.
11. The semiconductor device as recited in claim 10 , wherein the dopants include at least one of boron and boron difluoride dopants.
12. The semiconductor device as recited in claim 10 , wherein the buried conductive channel layer includes arsenic dopants.
13. A semiconductor device, comprising:
a transistor device formed in a substrate adjacent to an isolation region, the transistor device comprising a junction region activated by a gate conductor to conduct charge through the junction region, the junction region extending from a surface of the substrate to a first depth;
a region disposed between the junction region and the isolation region including an area susceptible to charge trapping; and
a charge injection region formed in the junction to provide a peak charge transfer layer through the junction region, the charge injection region having a peak conduction depth which is different than a depth of the area susceptible to charge trapping,
wherein the region disposed between the junction region and the isolation region includes a divot disposed between the junction region and the isolation region, the divot being filled by the gate conductor.
14. The semiconductor device as recited in claim 13 , wherein the isolation region includes a shallow trench isolation region.
15. The semiconductor device as recited in claim 14 , wherein the shallow trench isolation region includes a nitride liner and the area susceptible to charge trapping includes an area between the nitride liner and the junction region.
16. The semiconductor device as recited in claim 13 , wherein the charge injection region includes a buried conductive channel layer.
17. The semiconductor device as recited in claim 13 , wherein the charge injection region includes dopants.
18. The semiconductor device as recited in claim 17 , wherein the dopants include at least one of boron and boron difluoride dopants.
19. The semiconductor device as recited in claim 13 , wherein the buried conductive channel layer includes arsenic dopants.