Patent Assignment
Reel/Frame 023788/0535
Assignment of Assignor's Interest
Recorded: 2010-01-14
Received: 2010-01-14
Pages: 389
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, DEX, 81739, GERMANY
Covered Properties
(97)
Ferromagnetic Liner for Conductive Lines of Magnetic Memory Cells
Application:
11/644,792 →
Magnetic Switching Device
Application:
11/070,856 →
Selective Etching to Increase Trench Surface Area
Application:
11/047,312 →
Method and Apparatus for Current Sense Amplifier Calibration in Mram Devices
Application:
10/905,585 →
Method of Fabricating a Bottle Trench and a Bottle Trench Capacitor
Application:
10/904,582 →
Encapsulation of Conductive Lines of Semiconductor Devices
Application:
10/898,858 →
Ferromagnetic Liner for Conductive Lines of Magnetic Memory Cells and Methods of Manufacturing Thereof
Application:
10/899,488 →
Mtj Patterning Using Free Layer Wet Etching and Lift Off Techniques
Application:
10/890,767 →
Techniques for Reducing Neel Coupling in Toggle Switching Semiconductor Devices
Application:
10/878,156 →
Methods of Patterning a Magnetic Stack of a Magnetic Memory Cell and Structures Thereof
Application:
10/870,756 →
Mask Schemes for Patterning Magnetic Tunnel Junctions
Application:
10/868,328 →
Method of Patterning a Magnetic Tunnel Junction Stack for a Magneto-Resistive Random Access Memory
Application:
10/709,999 →
Single Exposure of Mask Levels Having a Lines and Spaces Array Using Alternating Phase-Shift Mask
Application:
10/846,275 →
Magnetic Tunnel Junction Cap Structure and Method for Forming the Same
Application:
10/709,573 →
Field Ramp Down for Pinned Synthetic Antiferromagnet
Application:
10/835,623 →
Magnetic Tunnel Junctions for Mram Devices
Application:
10/785,913 →
Line Mask Defined Active Areas for 8F2 Dram Cells with Folded Bit Lines and Deep Trench Patterns
Application:
10/774,827 →
Method of forming a trench structure
Application:
10/708,035 →
Method of Making Encapsulated Spacers in Vertical Pass Gate Dram and Damascene Logic Gates
Application:
10/770,264 →
Precharging the Write Path of an Mram Device for Fast Write Operation
Application:
10/758,449 →
Nitrided Sti Liner Oxide for Reduced Corner Device Impact on Vertical Device Performance
Application:
10/707,754 →
System and Method for Variable Array Architecture for Memories
Application:
10/748,333 →
Deep Trench Capacitor with Buried Plate Electrode and Isolation Collar
Application:
10/741,203 →
Clean chemistry for tungsten/tungsten nitride gates
Application:
10/718,381 →
Method for Performing a Burn-in Test
Application:
10/605,927 →
Method for Fast and Local Anneal of Anti-Ferromagnetic (Af) Exchange-Biased Magnetic Stacks
Application:
10/690,538 →
Inclusion of Low-K Dielectric Material Between Bit Lines
Application:
10/689,233 →
Semiconductor Device Cleaning Employing Heterogeneous Nucleation for Controlled Cavitation
Application:
10/685,684 →
Self-Aligned Array Contact for Memory Cells
Application:
10/605,590 →
Mram Array Having a Segmented Bit Line
Application:
10/679,160 →
Top Oxide Nitride Liner Integration Scheme for Vertical Dram
Application:
10/605,438 →
Fabrication Process for a Magnetic Tunnel Junction Device
Application:
10/659,136 →
Fuse Latch Circuit with Non-Disruptive Re-Interrogation
Application:
10/657,362 →
Bulk Contact Mask Process
Application:
10/605,087 →
Reduced Cap Layer Erosion for Borderless Contacts
Application:
10/655,199 →
Self-Aligned Drain/Channel Junction in Vertical Pass Transistor Dram Cell Design for Device Scaling
Application:
10/604,731 →
Method of Fabricating a Buried Collar
Application:
10/604,562 →
Magnetic Random Access Memory and Method of Fabricating Thereof
Application:
10/604,533 →
Method and Apparatus for Amplitude Filtering in the Frequency Plane of a Lithographic Projection System
Application:
10/604,519 →
Dram Buried Strap Process with Silicon Carbide
Application:
10/604,488 →
Recessed Metal Lines for Protective Enclosure in Integrated Circuits
Application:
10/610,609 →
Gate Length Proximity Corrected Device
Application:
10/604,112 →
Self-Aligned Mask to Reduce Cell Layout Area
Application:
10/600,034 →
Maskless Array Protection Process Flow for Forming Interconnect Vias in Magnetic Random Access Memory Devices
Application:
10/250,133 →
Methods and Apparatus for Providing an Antifuse Function
Application:
10/447,018 →
Circuit Configuration for a Current Switch of a Bit/Word Line of a Mram Device
Application:
10/445,550 →
Critical Dimension Control of Printed Features Using Non-Printing Fill Patterns
Application:
10/425,817 →
Adhesion Layer for Pt on SIO2
Application:
10/408,339 →
Method of Reducing Pitch on Semiconductor Wafer
Application:
10/406,888 →
Method of Reducing Erosion of a Nitride Gate Cap Layer During Reactive Ion Etch of Nitride Liner Layer for Bit Line Contact of Dram Device
Application:
10/406,645 →
Layout Impact Reduction with Angled Phase Shapes
Application:
10/249,317 →
Trench Isolation Employing a Doped Oxide Trench Fill
Application:
10/397,761 →
Method to Fill Deep Trench Structures with Void-Free Polysilicon or Silicon
Application:
10/386,880 →
Suppressing Lithography at a Wafer Edge
Application:
10/248,911 →
Carbon-Graded Layer for Improved Adhesion of Low-K Dielectrics to Silicon Substrates
Application:
10/366,149 →
Two-Step Magnetic Tunnel Junction Stack Deposition
Application:
10/348,235 →
Reduced Hot Carrier Induced Parasitic Sidewall Device Activation in Isolated Buried Channel Devices by Conductive Buried Channel Depth Optimization
Application:
10/338,517 →
Buried Strap with Limited Outdiffusion and Vertical Transistor Dram
Application:
10/336,988 →
Teos Assisted Oxide Cmp Process
Application:
10/314,865 →
Orientation Independent Oxidation of Nitrided Silicon
Application:
10/284,508 →
Techniques for Electrically Characterizing Tunnel Junction Film Stacks with Little or No Processing
Application:
10/244,766 →
Vertical Hard Mask
Application:
10/241,225 →
Low Cu Percentages for Reducing Shorts in Alcu Lines
Application:
10/207,773 →
Method to Enhance Epi-Regrowth in Amorphous Poly Cb Contacts
Application:
10/206,875 →
Low Resistivity Deep Trench Fill for Dram and Edram Applications
Application:
10/142,518 →
Repeater with Reduced Power Consumption
Application:
10/114,195 →
Low Voltage Level Shifter with Latching Function
Application:
10/114,221 →
Vertical Mosfet with Horizontally Graded Channel Doping
Application:
10/096,219 →
Novel Method to Achieve Increased Trench Depth, Independent of Cd as Defined by Lithography
Application:
10/093,789 →
Multiple Finger Off Chip Driver (Ocd) with Single Level Translator
Application:
10/093,784 →
Trench Isolation Processes Using Polysilicon-Assisted Fill
Application:
10/083,744 →
Method for Surface Roughness Enhancement in Semiconductor Capacitor Manufacturing
Application:
10/016,075 →
Process for Forming a Damascene Structure
Application:
09/994,340 →
Method of Manufacturing 6F2 Trench Capacitor Dram Cell Having Vertical Mosfet and 3F Bitline Pitch
Application:
10/011,556 →
Recess Pt Structure for High K Stacked Capacitor in Dram and Fram, and the Method to Form This Structure
Application:
09/982,574 →
Methods for Crystallizing Metallic Oxide Dielectric Films at Low Temperature
Application:
09/966,496 →
Gate Processing Method with Reduced Gate Oxide Corner and Edge Thinning
Application:
09/965,919 →
Liner with Poor Step Coverage to Improve Contact Resistance in W Contacts
Application:
09/965,094 →
Unit-Architecture with Implemented Limited Bank-Column-Select Repairability
Application:
09/964,208 →
Method of Forming a Self Aligned Trench in a Semiconductor Using a Patterned Sacrificial Layer for Defining the Trench Opening
Application:
09/957,937 →
Pre-Charge Circuit and Method for Memory Devices with Shared Sense Amplifiers
Application:
09/941,911 →
Method for Low Temperature Chemical Vapor Deposition of Low-K Films Using Selected Cyclosiloxane and Ozone Gases for Semiconductor Applications
Application:
09/928,209 →
Grating Patterns and Method for Determination of Azimuthal and Radial Aberration
Application:
09/916,917 →
Mosfet Having a Low Aspect Ratio Between the Gate and the Source/Drain
Application:
09/911,894 →
Carbon-Graded Layer for Improved Adhesion of Low-K Dielectrics to Silicon Substrates
Application:
09/910,380 →
Structure and Method of Fabricating Embedded Vertical Dram Arrays with Silicided Bitline and Polysilicon Interconnect
Application:
09/897,868 →
Method of Etching High Aspect Ratio Openings
Application:
09/874,109 →
Compact Trench Capacitor Memory Cell with Body Contact
Application:
09/866,278 →
Contact Plug Formation for Devices with Stacked Capacitors
Application:
09/861,253 →
Vertical Gate Top Engineering for Improved Gc and Cb Process Windows
Application:
09/837,799 →
Tto Nitride Liner for Improved Collar Protection and Tto Reliability
Application:
09/832,605 →
Semiconductor Memory Having Asymmetric Column Addressing and Twisted Read Write Drive (Rwd) Line Architecture
Application:
09/795,761 →
Multi-Level Fuse Structure
Application:
09/772,377 →
Method and apparatus for the replacement of non-operational metal lines in DRAMS
Application:
09/764,816 →
Structure and Method of Forming Bitline Contacts for a Vertical Dram Array Using a Line Bitline Contact Mask
Application:
09/764,833 →
Vertical Mosfet
Application:
09/757,514 →
Method for Dry Etching Deep Trenches in a Substrate
Application:
09/757,123 →