Self-aligned array contact for memory cells
View Patent ↗A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.
1. An integrated circuit comprising:
a substrate having a single-crystal semiconductor region defining a major surface of said substrate;
a plurality of first transistors having conduction channels disposed in a memory cell array region of said semiconductor region;
a plurality of second transistors having conduction channels disposed in an external region of said semiconductor region outside of said memory cell array region;
a dielectric region covering said first transistors and said second transistors, said dielectric region having a plurality of troughs, each said trough having a pair of vertical sidewalls, each said sidewall extending substantially in a single plane to said substrate;
a plurality of bitline contacts disposed in said troughs, said bitline contacts including a plurality of conductive vias extending in a vertical direction normal to said major surface to contact said first transistors;
a plurality of horizontally extending bitlines disposed in said troughs and conductively connected to said conductive vias, said bitlines extending over said memory cell array region in a horizontal direction substantially parallel to said major surface; and
metallic conductive lines interconnecting said bitlines to said second transistors, said conductive lines differing from said bitlines in a patterned characteristic including at least one of horizontal width, vertical thickness, and placement relative to said bitlines.
2. The integrated circuit of claim 1 wherein said bitlines are interconnected to said conductive lines by a plurality of horizontally disposed conductive interconnections, said conductive interconnections differing from said bitlines in a pattern characteristic including at least one of horizontal width, vertical thickness, and placement relative to said bitlines.
3. The integrated circuit of claim 2 further comprising wordlines encapsulated by insulative material, wherein said conductive vias of said bitline contacts include borderless contacts disposed between said encapsulated wordlines.
4. The integrated circuit of claim 3 wherein said conductive vias of said bitline contacts include at least a first layer consisting essentially of polysilicon and said bitlines include at least a second layer consisting essentially of at least one material selected from the group consisting of metals and conductive compounds of metals.
5. The integrated circuit of claim 3 wherein said bitlines and said conductive vias of said bitline contacts consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals.
6. The integrated circuit of claim 5 wherein said conductive lines are broader than said bitlines where said conductive lines interconnect to said bitlines.
7. The integrated circuit of claim 6 wherein said conductive lines interconnect pairs of said bitlines to sense amplifiers located in a plurality of said external regions disposed beyond opposite edges of said memory cell array, wherein successive pairs of said bitlines are coupled to sense amplifiers located in alternating ones of said external regions.
8. The integrated circuit of claim 7 wherein said conductive interconnections are disposed over isolation structures, said isolation structures isolating said memory cell array region from said external regions.