Reduced cap layer erosion for borderless contacts

1. A method of manufacturing a borderless contact, the method comprising:

providing a workpiece, the workpiece having at least one component region and a first insulating layer formed over the at least one component region;

depositing a first conductive material over the workpiece;

depositing a first etch selectivity material over the first conductive material;

depositing a second etch selectivity material over the first etch selectivity material;

etching the second etch selectivity material, the first etch selectivity material and the first conductive material to form a plurality of first conductive lines, the second etch selectivity material, first etch selectivity material and first conductive lines comprising sidewalls, the second etch selectivity material comprising a top surface;

forming sidewall spacers on the sidewalls of the second etch selectivity material, first etch selectivity material and first conductive lines;

depositing a liner over exposed portions of the workpiece, the sidewall spacers and the second etch selectivity material top surface;

depositing a second insulating layer over the liner to a height greater than the top surface of the second etch selectivity material;

patterning the second insulating layer with a pattern for a plurality of second conductive lines, the second conductive lines being positioned in a different direction than the first conductive lines;

removing the liner from at least over the component region;

removing the first insulating layer from over the component region; and

depositing a second conductive material over the second insulating layer to fill the pattern for the plurality of second conductive lines, forming a plurality of second conductive lines and a borderless contact beneath at least one second conductive line abutting the at least one component region.

2. The method according to claim 1 , wherein removing the first insulating layer from over the component region comprises an etch process selective to the first etch selectivity material, wherein removing the first insulating layer further comprises removing the second etch selectivity material.

3. The method according to claim 1 , wherein depositing the first etch selectivity material comprises depositing a nitride or silicon oxycarbide.

4. The method according to claim 3 , wherein depositing the first etch selectivity material comprises depositing silicon nitride.

5. The method according to claim 1 , wherein depositing the second etch selectivity material comprises depositing an oxide or silicon oxycarbide.

6. The method according to claim 5 , wherein depositing the second etch selectivity material comprises depositing silicon dioxide.

7. The method according to claim 1 , wherein forming sidewall spacers comprises:

depositing an insulating material with the same etch selectivity as the first etch selectivity material over the second etch selectivity material and exposed portions of the workpiece; and

anisotropically etching the insulating material.

8. The method according to claim 7 , wherein depositing the insulating material comprises depositing silicon nitride.

9. The method according to claim 1 , wherein depositing the first conductive material comprises depositing a silicide.

10. The method according to claim 1 , further comprising forming a thin oxide layer over the sidewalls of the first conductive lines, prior to forming the sidewall spacers.

11. The method according to claim 1 , wherein depositing the first insulating layer comprises depositing a layer of borophosphosilicate glass (BPSG) over the liner and depositing a layer of tetraethoxysilate (TEOS) over the BPSG glass layer.

12. The method according to claim 1 , wherein depositing the liner comprises depositing silicon nitride.

13. The method according to claim 1 , wherein the at least one component region comprises a memory cell.

14. The method according to claim 1 , wherein the at least one component region comprises an access transistor for a memory cell.

15. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece, the workpiece having a plurality of component regions and a first insulating layer formed over the component regions;

depositing a first conductive material over the workpiece;

depositing a first etch selectivity material over the first conductive material;

depositing a second etch selectivity material over the first etch selectivity material;

etching the second etch selectivity material, the first etch selectivity material and the first conductive material to form a plurality of first conductive lines, the second etch selectivity material, first etch selectivity material and first conductive lines comprising sidewalls, the second etch selectivity material comprising a top surface;

depositing a second insulating layer having the same etch selectivity as the first etch selectivity material over the second etch selectivity material and exposed portions of the workpiece;

anisotropically etching the second insulating layer to form sidewall spacers on the sidewalls of the second etch selectivity material, first etch selectivity material and first conductive lines;

depositing a nitride liner over exposed portions of the workpiece, the sidewall spacers and the second etch selectivity material top surface;

depositing a third insulating layer over the nitride liner to a height greater than the top surface of the second etch selectivity material;

patterning the third insulating layer with a pattern for a plurality of second conductive lines, the second conductive lines being positioned in a different direction than the first conductive lines;

removing the nitride liner from the component regions;

removing the first insulating layer from over the component region using an etch process selective to the first etch selectivity material, also removing a portion of the second etch selectivity material; and

depositing a second conductive material over the second insulating layer to fill the pattern for the plurality of second conductive lines, forming a plurality of second conductive lines and a borderless contact beneath at least one second conductive line abutting the at least one component region.

16. The method according to claim 15 , wherein depositing the first etch selectivity material comprises depositing a nitride or silicon oxycarbide.

17. The method according to claim 16 , wherein depositing the first etch selectivity material comprises depositing silicon nitride.

18. The method according to claim 15 , wherein depositing the second etch selectivity material comprises depositing an oxide or silicon oxycarbide.

19. The method according to claim 18 , wherein depositing the second etch selectivity material comprises depositing silicon dioxide.

20. The method according to claim 15 , wherein depositing the second insulating layer comprises depositing silicon nitride.

21. The method according to claim 15 , wherein depositing the first conductive material comprises depositing a silicide.

22. The method according to claim 15 , further comprising forming a thin oxide layer over the sidewalls of the first conductive lines, prior to forming the sidewall spacers.

23. The method according to claim 15 , wherein depositing the third insulating layer comprises depositing a layer of borophosphosilicate glass (BPSG) over the liner and depositing a layer of tetraethoxysilate (TEOS) over the BPSG glass layer.

24. The method according to claim 15 , wherein the component regions comprise memory cells.

25. The method according to claim 15 , wherein the component regions comprise access transistors for memory cells.