Adhesion layer for Pt on SiO
View Patent ↗Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO 2 ) substrate in capacitor structures of memory devices.
1. An adhesion layer, comprising:
at least one layer of Si in contact with a noble metal layer and in contact with a silicon dioxide (SiO 2 ) layer.
2. The adhesion layer recited in claim 1 wherein the noble metal layer comprises Pt.
3. The adhesion layer recited in claim 1 wherein the noble metal layer is an electrode of a high-k dielectric capacitor.
4. The adhesion layer recited in claim 3 wherein the capacitor is included in a memory device.
5. In a semiconductor capacitor structure formed on a silicon dioxide (SiO 2 ) layer and having a noble metal electrode, the structure comprising:
an adhesion layer of Si disposed between the noble metal electrode and the SiO 2 layer and adhering to the noble metal electrode and to the SiO2 layer.
6. The structure recited in claim 5 wherein the noble metal electrode comprises Pt.
7. The structure recited in claim 5 wherein the capacitor structure is included in a memory device.
8. The structure recited in claim 5 wherein the adhesion layer is IrO 2 .
9. A memory device, comprising:
a silicon dioxide (SiO 2 ) layer;
a capacitor comprising a noble metal electrode formed on the SiO 2 layer; and
a Si adhesion layer disposed between and in physical contact with the noble metal electrode and the SiO 2 layer.
10. The memory device recited in claim 9 wherein the noble metal electrode comprises Pt.
11. The memory device recited in claim 9 wherein the capacitor includes a high-k dielectric layer disposed on the noble metal electrode.
12. The memory device recited in claim 11 wherein the capacitor comprises another electrode disposed on the high-k dielectric layer.
13. An adhesion layer, comprising:
a Si layer disposed between and adhering to a noble metal layer and a silicon oxide layer.
14. The adhesion layer recited in claim 13 wherein the noble metal layer comprises Pt.
15. The adhesion layer recited in claim 13 wherein the noble metal layer is an electrode of a high-k dielectric capacitor.
16. The adhesion layer recited in claim 15 wherein the capacitor is included in a memory device.
17. The adhesion layer recited in claim 13 wherein the silicon oxide layer comprises SiO 2 .
18. In a semiconductor capacitor structure formed on a silicon oxide layer and having a noble metal electrode, the structure comprising:
a Si adhesion layer physically contacting both the noble metal electrode and the silicon oxide layer.
19. The structure recited in claim 18 wherein the noble metal electrode comprises Pt.
20. The structure recited in claim 18 wherein the capacitor structure is included in a memory device.
21. A memory device, comprising:
a silicon oxide layer;
a capacitor comprising a noble metal electrode formed on the silicon oxide layer; and
an adhesion layer comprised of Si disposed between and adhering to the noble metal electrode and the silicon oxide layer, the Si adhesion layer deposited on the silicon oxide layer and the noble metal electrode deposited on the Si adhesion layer.
22. The memory device recited in claim 21 wherein the noble metal electrode comprises Pt.
23. The memory device recited in claim 21 wherein the capacitor includes a high-k dielectric layer disposed on the noble metal electrode.
24. The memory device recited in claim 23 wherein the capacitor comprises another electrode disposed on the high-k dielectric layer.