Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns
View Patent ↗A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.
1. A semiconductor memory device comprising:
an array of memory cells arranged in an array of rows and columns at a surface of a semiconductor body, each memory cell comprising:
a trench disposed within the semiconductor body;
a conductive material filling at least a lower portion of the trench;
a dielectric material lining sidewalls of the trench such that the conductive material filling the trench forms a first plate of a capacitor and semiconductor material of the semiconductor body forms a second plate of the capacitor, the second plate of the capacitor being electrically coupled to capacitors of other memory cells within the array;
a trench collar lining a portion of a sidewall of the trench above the dielectric material;
a pass transistor having a first source/drain region and a second source/drain region, the first source/drain region being electrically coupled to the conductive material through an opening in the trench collar, the opening formed at one side of the trench such that an asymmetric trench structure is formed;
a plurality of wordlines extending along the rows of the array of memory cells, cach wordline being electrically coupled to a gate of every other memory cell along the row;
a plurality of bitlines extending along the columns of the array of memory cells, each bitline being electrically coupled to the second source/drain region of every other memory cell along the column; and
a plurality of isolation regions extending parallel to the plurality of bitlines and disposed between columns of the array of memory cells, each isolation region comprising a rectangular strip of insulating material that extends between adjacent columns of the memory cells, wherein adjacent ones of the memory cells within a column are isolated without use of the isolation regions.
2. The device of claim 1 , wherein each isolation region has a width and is separated from a parallel isolation by a spacing distance, wherein the width is equal to the spacing distance.
3. The device of claim 1 , wherein adjacent ones of the trenches are separated by a distance 3F, where F is a minimum feature size.
4. The device of claim 1 , wherein each pass transistor comprises a vertical transistor.
5. The device of claim 1 , wherein, for each memory cell, the second source/drain region is located at the surface of the semiconductor body and the first source/drain region is located within the semiconductor body spaced from the surface.
6. The device of claim 1 , wherein the conductive material filling at least the lower portion of the trench comprises doped polysilicon.
7. The device of claim 1 , wherein the second plate of the capacitor comprises a doped region of the semiconductor body that extends beneath ones of the trenches.