Phase change memory cell design with adjusted seam location

1. A memory cell comprising:

a lower electrode, the lower electrode comprising a first surface region and a second surface region, the second surface region raised in relation to first surface region;

a phase change feature, the phase change feature disposed on the second surface region of the lower electrode and comprising a phase change material and one or more sidewalls;

a spacer feature, the spacer feature disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature; and

a dielectric layer, the dielectric layer disposed at least partially on the first surface region of the lower electrode and abutting the spacer feature.

2. The memory cell of claim 1 , wherein the phase change feature and the spacer feature occupy substantially the whole of the second surface region of the lower electrode.

3. The memory cell of claim 1 , wherein the lower electrode comprises titanium nitride, tantalum nitride, tungsten, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, tantalum aluminum nitride, or carbon, or a combination thereof.

4. The memory cell of claim 1 , wherein the phase change feature comprises germanium, antimony, sulfur, selenium, or tellurium, or a combination thereof.

5. The memory cell of claim 1 , wherein the phase change feature comprises a transition metal oxide.

6. The memory cell of claim 1 , wherein the spacer feature comprises silicon dioxide or silicon nitride.

7. The memory cell of claim 1 , wherein the dielectric layer comprises silicon dioxide or silicon nitride.

8. The memory cell of claim 1 , further comprising an upper electrode, the upper electrode disposed on the phase change feature.

9. The memory cell of claim 8 , wherein the lower and upper electrodes are adapted to pass an electrical signal through the phase change feature in order to cause at least a portion of the phase change feature to change phase.

10. The memory cell of claim 1 , wherein the dielectric layer comprises a seam.

11. A method of forming a memory cell, the method comprising the steps of:

forming a lower electrode, the lower electrode comprising a first surface region and a second surface region, the second surface region raised in relation to first surface region;

forming a phase change feature, the phase change feature disposed on the second surface region of the lower electrode and comprising a phase change material and one or more sidewalls;

forming a spacer feature, the spacer feature disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature; and

forming a dielectric layer, the dielectric layer disposed at least partially on the first surface region of the lower electrode and abutting the spacer feature.

12. The method of claim 11 , wherein the step of forming a spacer feature comprises depositing a layer of spacer material and anisotropically etching the layer of spacer material.

13. The method of claim 12 , wherein anisotropically etching comprises reactive ion etching.

14. The method of claim 11 , wherein the step of forming the lower electrode comprises defining the first and second surface regions of the lower electrode by anisotropic etching.

15. The method of claim 14 , wherein the spacer feature and the phase change feature are used as a mask while defining the first and second surface regions of the lower electrode by anisotropic etching.

16. The method of claim 11 , wherein the step of forming the dielectric layer comprises chemical vapor deposition.

17. The method of claim 11 , wherein the step of forming the dielectric layer comprises chemical-mechanical polishing.

18. An integrated circuit comprising one or more memory cells, at least one of the one or more memory cells comprising:

a lower electrode, the lower electrode comprising a first surface region and a second surface region, the second surface region raised in relation to first surface region;

a phase change feature, the phase change feature disposed on the second surface region of the lower electrode and comprising a phase change material and one or more sidewalls;

a spacer feature, the spacer feature disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature; and

a dielectric layer, the dielectric layer disposed at least partially on the first surface region of the lower electrode and abutting the spacer feature.

19. The integrated circuit of claim 18 , wherein the integrated circuit comprises a random access memory.

20. The integrated circuit of claim 18 , wherein the integrated circuit comprises a nonvolatile memory.