IP Library Assignment 023791/0001
Patent Assignment
Reel/Frame 023791/0001

Assignment of Assignor's Interest

Recorded: 2010-01-14 Pages: 387
Assignor
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81739, GERMANY
Covered Properties (56)
Textured Bi-Based Oxide Ceramic Films
Patent: 6,713,797 →
Application: 09/197,984 →
Reduced Diffusion of a Mobile Specie from a Metal Oxide Ceramic into the Substrate
Patent: 6,204,158 →
Application: 09/216,371 →
Driver Circuit with Negative Lower Power Rail
Patent: 6,127,878 →
Application: 09/225,664 →
Contact and Deep Trench Patterning
Patent: 6,204,187 →
Application: 09/226,434 →
Method for Manufacturing Memory Cell with Trench Capacitor
Patent: 6,143,599 →
Application: 09/235,621 →
Delay-Locked-Loop (Dll) Having Symmetrical Rising and Falling Clock Edge Type Delays
Patent: 6,127,866 →
Application: 09/239,487 →
Field-Shield-Trench Isolation for Gigabit Drams
Patent: 6,762,447 →
Application: 09/245,269 →
Shallow Trench Isolation (Sti) with Bilayer of Oxide-Nitride for Vlsi Applications
Patent: 6,140,208 →
Application: 09/245,958 →
Current Source
Patent: 6,087,820 →
Application: 09/265,252 →
Capacitive Coupled Driver Circuit
Patent: 6,215,349 →
Application: 09/265,253 →
Capacitor Trench-Top Dielectric for Self-Aligned Device Isolation
Patent: 6,184,107 →
Application: 09/271,124 →
Memory Cell Layout for Reduced Interaction Between Storage Nodes and Transistors
Patent: 6,211,544 →
Application: 09/272,215 →
Frequency Range Trimming for a Delay Line
Patent: 6,229,364 →
Application: 09/274,633 →
Dynamic Random Access Memory
Patent: 6,204,140 →
Application: 09/275,337 →
Apparatus and Method for Performing a Defect Leakage Screen Test for Memory Devices
Patent: 6,330,697 →
Application: 09/294,866 →
Delay Element Using a Delay Locked Loop
Patent: 6,252,443 →
Application: 09/295,157 →
Formation of 5F2 Cell with Partially Vertical Transistor and Gate Conductor Aligned Buried Strap with Raised Shallow Trench Isolation Region
Patent: 6,190,971 →
Application: 09/311,471 →
System for Dispensing Polishing Liquid During Chemical Mechanical Polishing of a Semiconductor Wafer
Patent: 6,225,224 →
Application: 09/315,090 →
Temperature Controlled Gassification of Deionized Water for Megasonic Cleaning of Semiconductor Wafers
Patent: 6,295,998 →
Application: 09/318,155 →
Temperature Controlled Degassification of Deionized Water for Megasonic Cleaning of Semiconductor Wafers
Patent: 6,167,891 →
Application: 09/318,156 →
Hydrogen Peroxide and Acid Etchant for a Wet Etch Process
Patent: 6,379,577 →
Application: 09/329,894 →
Publication: US 2001/0037995
Hierarchical Prefetch for Semiconductor Memories
Patent: 6,081,479 →
Application: 09/333,539 →
Transistors Having Independently Adjustable Parameters
Patent: 6,501,131 →
Application: 09/359,291 →
Crystal-Axis-Aligned Vertical Side Wall Device
Patent: 6,320,215 →
Application: 09/359,292 →
Mixed Fuse Technologies
Patent: 6,288,436 →
Application: 09/361,960 →
Vertical Dram Cell with Wordline Self-Aligned to Storage Trench
Patent: 6,153,902 →
Application: 09/374,687 →
Silylation Method for Reducing Critical Dimension Loss and Resist Loss
Patent: 6,107,177 →
Application: 09/382,933 →
Disposable Spacers for Improved Array Gapfill in High Density Drams
Patent: 6,281,084 →
Application: 09/386,832 →
Fill Strategies in the Optical Kerf
Patent: 6,396,160 →
Application: 09/395,420 →
Improved Metal Line Deposition Process
Patent: 6,136,709 →
Application: 09/413,265 →
High Dielectric Constant Material Deposition to Achieve High Capacitance
Patent: 6,207,584 →
Application: 09/478,270 →
Method to prevent oxygen Out-Diffusion from BSTO containing Micro-Electronic device
Patent: 6,214,661 →
Application: 09/489,771 →
Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods therefor
Patent: 6,359,471 →
Application: 09/491,645 →
Easy to remove hard mask layer for semiconductor device fabrication
Patent: 6,261,967 →
Application: 09/501,479 →
Data Path Calibration and Testing Mode Using a Data Bus for Semiconductor Memories
Patent: 6,799,290 →
Application: 09/512,756 →
Semiconductor Structure and Manufacturing Method
Patent: 6,365,328 →
Application: 09/522,883 →
Cbr refresh control for the redundancy array
Patent: 6,195,300 →
Application: 09/536,185 →
System for dispensing polishing liquid during chemical mechanical polishing of a semiconductor wafer
Patent: 6,264,789 →
Application: 09/562,218 →
Electrical fuses employing reverse biasing to enhance programming
Patent: 6,323,535 →
Application: 09/595,764 →
Design Layout for a Dense Memory Cell Structure
Patent: 6,396,096 →
Application: 09/597,401 →
Process Flow for Capacitance Enhancement in a Dram Trench
Patent: 6,555,430 →
Application: 09/723,420 →
Embedded vertical dram cells and dual workfunction logic gates
Patent: 6,258,659 →
Application: 09/725,412 →
Method of Reducing Sub-Threshold Leakage in Circuits During Standby Mode
Patent: 6,522,171 →
Application: 09/759,011 →
Publication: US 2002/0089352
Dynamic Dram Refresh Rate Adjustment Based on Cell Leakage Monitoring
Patent: 6,483,764 →
Application: 09/761,045 →
Publication: US 2002/0136075
Low Bitline Capacitance Structure and Method of Making Same
Patent: 6,426,247 →
Application: 09/764,824 →
Structure and Method for Improved Isolation in Trench Storage Cells
Patent: 6,437,401 →
Application: 09/824,957 →
Method to Increase Removal Rate of Oxide Using Fixed-Abrasive
Patent: 6,485,355 →
Application: 09/887,790 →
Publication: US 2002/0197937
Modified Vertical Mosfet and Methods of Formation Thereof
Patent: 6,541,810 →
Application: 09/896,741 →
Publication: US 2003/0001200
Method of Forming Low-Leakage on-Chip Capacitor
Patent: 6,451,662 →
Application: 09/970,635 →
Low k dielectric film deposition process
Application: 10/005,861 →
Publication: US 2003/0087043
Twisted Bit-Line Compensation for Dram Having Redundancy
Patent: 6,570,794 →
Application: 10/034,626 →
Rtcvd Process and Reactor for Improved Conformality and Step-Coverage
Patent: 6,576,565 →
Application: 10/075,152 →
Self-Aligned Buried Strap Process Using Doped Hdp Oxide
Patent: 6,667,504 →
Application: 10/249,228 →
Process Flow for Thick Isolation Collar with Reduced Length
Patent: 6,605,838 →
Application: 10/261,219 →
Architecture for High-Speed Magnetic Memories
Patent: 6,778,431 →
Application: 10/318,709 →
Publication: US 2004/0114439
Self-Aligned Buried Strap Process Using Doped Hdp Oxide
Patent: 6,946,345 →
Application: 10/688,612 →
Publication: US 2004/0188740
Related Assignments (18)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest May 1, 2014
From: ENTEGRIS, INC.; POCO GRAPHITE, INC.; ATMI, INC.; ADVANCED TECHNOLOGY MATERIALS, INC.
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 032815/0852 →
Security Interest May 2, 2014
From: ENTEGRIS, INC.; POCO GRAPHITE, INC.; ATMI, INC.; ADVANCED TECHNOLOGY MATERIALS, INC.
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 032812/0192 →
Assignment of Assignor's Interest Feb 4, 2015
From: ADVANCED TECHNOLOGY MATERIALS, INC.
To: ENTEGRIS, INC.
Reel/Frame 034894/0025 →
Assignment of Assignor's Interest May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Assignment of Assignor's Interest Dec 7, 2015
From: INFINEON TECHNOLOGIES AG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037221/0885 →
Release of Security Interest Nov 8, 2018
From: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
To: ENTEGRIS, INC.; POCO GRAPHITE, INC.; ATMI, INC.; ATMI PACKAGING, INC.
Reel/Frame 047477/0151 →
Release of Security Interest Nov 8, 2018
From: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
To: ENTEGRIS, INC.; POCO GRAPHITE, INC.; ATMI, INC.; ATMI PACKAGING, INC.
Reel/Frame 047477/0032 →
Security Interest Nov 13, 2018
From: ENTEGRIS, INC.; SAES PURE GAS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 048811/0679 →
Security Agreement Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
Assignment of Assignor's Interest Aug 21, 2019
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 050122/0001 →
Assignment of Patent Security Interest Recorded at Reel/Frame 048811/0679 Nov 5, 2019
From: GOLDMAN SACHS BANK USA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 050965/0035 →
Assignment of Assignor's Interest Nov 20, 2019
From: GLOBALFOUNDRIES U.S. INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051070/0625 →
Assignment of Assignor's Interest Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
Assignment of Assignor's Interest Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
Release of Security Interest Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
Release of Security Interest May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →