IP Library Granted Patent US 6,946,345
Granted Patent B2
US 6,946,345 · App. 10/688,612 · Granted Sep 20, 2005

Self-aligned buried strap process using doped HDP oxide

Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 6,946,345
App. No.
10/688,612
Granted
Sep 20, 2005
Kind
B2
Abstract

The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

Claims (21)

1. A method of forming a memory device, said method comprising:

patterning a trench in a substrate;

filling a lower portion of said trench with a capacitor conductor;

forming a conductive buried strap in said substrate adjacent a top portion of said capacitor conductor;

forming a trench top oxide in said trench above said capacitor conductor, wherein said forming of said trench top oxide includes forming a doped trench top oxide layer above said capacitor conductor, and forming an undoped trench top oxide layer above said doped trench top oxide layer; and

after forming said first conductive buried strap and forming said doped trench top oxide, heating said device to form a second conductive buried strap in said substrate adjacent and connected to said first conductive buried strap; and

depositing a conductive node strap in said trench adjacent said capacitor conductor.

2. The method in claim 1 , wherein said process of depositing said doped trench top oxide layer comprises a high density plasma-chemical vapor deposition process.

3. The method in claim 1 , wherein during said process of depositing said doped trench top oxide layer a percentage by weight of dopant in said doped trench top oxide layer is less than 1%.

4. A method of forming a memory device, said method comprising:

patterning a trench in a substrate;

filling a lower portion of said trench with a capacitor conductor;

forming a doped material comprising first doping impurities adjacent a top of said capacitor conductor;

performing a first heating process to form a first conductive buried strap in said substrate adjacent a top portion of said capacitor conductor;

forming a doped trench top oxide comprising second doping impurities in said trench above said capacitor conductor; and

performing a second heating process to form a second conductive buried strap in said substrate adjacent and connected to said first conductive buried strap.

5. The method in claim 4 , wherein said process of forming said doped trench top oxide forms said doped trench top oxide to a level above a top of said first conductive buried strap.

6. The method in claim 4 , wherein said first conductive buried strap and said second conductive buried strap combine to form a conductive path.

7. The method in claim 4 , wherein said first conductive buried strap is formed from said first doping impurities outdiffusing into said substrate from said doped material and said second conductive buried strap is formed from said second doping impurities outdiffusing into said substrate from said doped trench top oxide.

8. The method in claim 4 , further comprising depositing an undoped trench top oxide in said trench above said doped trench top oxide.

9. The method in claim 8 , further comprising depositing a gate conductor in said trench above said undoped trench top oxide layer, wherein said undoped trench top oxide layer insulates said gate conductor from said capacitor conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION
To: QIMONDA AG
Reel/Frame 023791/0001 →
Continuity (2)
Division 1024922800 · Mar 24, 2003
Related Publication 20040188740A1 · Sep 30, 2004