Patent Assignment
Reel/Frame 050122/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2019-08-21
Received: 2019-08-21
Pages: 91
Assignor
GLOBALFOUNDRIES INC.
Executed: 2019-08-21
Assignee
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY, SANTA CLARA, CA, 95054, UNITED STATES
Covered Applications
(100)
FRANGIBLE FIREARM PROJECTILES, METHODS FOR FORMING THE SAME, AND FIREARM CARTRIDGES CONTAINING THE SAME
App. No. 16/547,407
→
COMMON BACKUP AND RECOVERY SOLUTION FOR DIVERSE CLOUD-BASED SERVICES IN A PRODUCTIVITY SUITE
App. No. 16/547,365
→
AUTOMATED TREND DETECTION
App. No. 16/547,182
→
UTILIZING DATA SOURCE IDENTIFIERS TO OBTAIN DEDUPLICATION EFFICIENCY WITHIN A CLUSTERED STORAGE ENVIRONMENT
App. No. 16/547,346
→
SYSTEM FOR HANDLING WORKPLACE QUERIES USING ONLINE LEARNING TO RANK
App. No. 16/521,244
→
CD79B CHIMERIC ANTIGEN RECEPTORS
PCTPCTUS2019037277
→
LOW-POWER SCAN FLIP-FLOP
App. No. 16/216,369
→
FEED FORWARD EQUALIZER WITH POWER-OPTIMIZED DISTRIBUTED ARITHMETIC ARCHITECTURE AND METHOD
App. No. 16/216,248
→
PARALLEL-PREFIX ADDER AND METHOD
App. No. 16/200,689
→
ULTRA-LOW VOLTAGE LEVEL SHIFTER
App. No. 16/189,407
→
LINEAR FEEDBACK SHIFT REGISTER-BASED CLOCK SIGNAL GENERATOR, TIME DOMAIN-INTERLEAVED ANALOG TO DIGITAL CONVERTER AND METHODS
App. No. 16/156,460
→
IC STRUCTURE INCLUDING TSV HAVING METAL RESISTANT TO HIGH TEMPERATURES AND METHOD OF FORMING SAME
App. No. 16/033,932
→
MIXING NOZZLE FITMENT
App. No. 16/065,379
→
INTEGRATED CIRCUIT (IC) DESIGN SYSTEMS AND METHODS USING SINGLE-PIN IMAGINARY DEVICES
App. No. 16/008,176
→
FAN-OUT CONNECTIONS OF PROCESSORS ON A PANEL ASSEMBLY
App. No. 15/988,638
→
MERGED WRITE DRIVER BASED ON LOCAL SOURCE LINE MRAM ARCHITECTURE
App. No. 15/983,263
→
CONTROL OF VCSEL-BASED OPTICAL COMMUNICATIONS SYSTEM
App. No. 15/982,459
→
COLUMN MULTIPLEXOR DECODING
App. No. 15/951,426
→
GIMBAL ASSEMBLY TEST SYSTEM AND METHOD
App. No. 15/933,443
→
DYNAMIC POWER ANALYSIS WITH PER-MEMORY INSTANCE ACTIVITY CUSTOMIZATION
App. No. 15/928,587
→
INTEGRATED LEVEL TRANSLATOR
App. No. 15/926,272
→
COMMON BOOSTED ASSIST
App. No. 15/906,588
→
ON-CHIP RELIABILITY MONITOR AND METHOD
App. No. 15/903,231
→
WRITE SCHEME FOR A STATIC RANDOM ACCESS MEMORY (SRAM)
App. No. 15/903,826
→
SENSE AMPLIFIER LATCH CIRCUIT AND SENSE AMPLIFIER MULTIPLEXED LATCH CIRCUIT
App. No. 15/895,001
→
CONTROLLING CURRENT FLOW BETWEEN NODES WITH ADJUSTABLE BACK-GATE VOLTAGE
App. No. 15/886,322
→
ELECTROSTATIC DISCHARGE CLAMP WITH REDUCED OFF-STATE POWER CONSUMPTION
App. No. 15/866,999
→
ANTENNA INSTALLATION INCLUDING AN ANTENNA LINE DEVICE CONTROLLABLE OVER A WIRELESS INTERFACE
App. No. 15/865,714
→
CHARGE PUMP CIRCUIT WITH BUILT-IN RETRY
App. No. 15/822,318
→
INTRACYCLE BITLINE RESTORE IN HIGH PERFORMANCE MEMORY
App. No. 15/814,969
→
INJECTION LOCKED OSCILLATOR SYSTEM AND PROCESSES
App. No. 15/801,735
→
TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS
App. No. 15/801,380
→
PEAKING AMPLIFIER FREQUENCY TUNING
App. No. 15/790,144
→
DIFFERENTIAL VOLTAGE GENERATOR
App. No. 15/788,289
→
HYBRID STACK WRITE DRIVER
App. No. 15/730,850
→
BIT LINE STRAPPING SCHEME FOR HIGH DENSITY SRAM
App. No. 15/693,637
→
MANAGING DATA FLOW IN VCSEL-BASED OPTICAL COMMUNICATIONS SYSTEM
App. No. 15/686,304
→
SENSE-LINE MUXING SCHEME
App. No. 15/684,492
→
TEST RESPONSE COMPACTION SCHEME
App. No. 15/668,362
→
INTERCONNECT STRUCTURE
App. No. 15/664,484
→
TRANSMITTER SYSTEM AND METHOD OF CALIBRATION
App. No. 15/659,352
→
REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TESTABLE IN SINGLE PASS
App. No. 15/636,793
→
PHASE ROTATOR APPARATUS
App. No. 15/629,900
→
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
App. No. 15/621,529
→
FLEXIBLE HEAT SPREADER LID
App. No. 15/593,969
→
ZERO TEST TIME MEMORY USING BACKGROUND BUILT-IN SELF-TEST
App. No. 15/478,666
→
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
App. No. 15/478,820
→
PEAKING AMPLIFIER FREQUENCY TUNING
App. No. 15/467,610
→
PEAKING AMPLIFIER FREQUENCY TUNING
App. No. 15/467,617
→
PEAKING AMPLIFIER FREQUENCY TUNING
App. No. 15/467,589
→
TRANSMISSION SYSTEM HAVING DUPLICATE TRANSMISSION SYSTEMS FOR INDIVIDUALIZED PRECHARGE AND OUTPUT TIMING
App. No. 15/464,397
→
ON-CHIP RESISTORS WITH A TUNABLE TEMPERATURE COEFFICIENT OF RESISTANCE
App. No. 15/460,914
→
FEEDBACK CIRCUIT AT WORDLINE ENDS
App. No. 15/451,470
→
WORDLINE DRIVER WITH INTEGRATED VOLTAGE LEVEL SHIFT FUNCTION
App. No. 15/446,091
→
MEMORY DEVICE STRUCTURE
App. No. 15/428,509
→
NON-GEOMETRIC SCALING CURRENT STEERING DIGITAL TO ANALOG CONVERTER
App. No. 15/412,193
→
CLOCK SYNCHRONIZATON USING CODEWORD MARKER
App. No. 15/406,350
→
NANOSECOND ACCURACY UNDER PRECISION TIME PROTOCOL FOR ETHERNET BY USING HIGH ACCURACY TIMESTAMP ASSIST DEVICE
App. No. 15/397,028
→
DIGITAL FREQUENCY MULTIPLIER TO GENERATE A LOCAL OSCILLATOR SIGNAL IN FDSOI TECHNOLOGY
App. No. 15/373,791
→
DIGITALLY CONTROLLED VARACTOR STRUCTURE FOR HIGH RESOLUTION DCO
App. No. 15/370,004
→
DISTRIBUTED CURRENT SOURCE/SINK USING INACTIVE MEMORY ELEMENTS
App. No. 15/363,056
→
BENDING CIRCUIT FOR STATIC RANDOM ACCESS MEMORY (SRAM) SELF-TIMER
App. No. 15/345,544
→
TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) FOR MULTI BIT MISS DETECT CIRCUIT
App. No. 15/340,579
→
ETHERNET PHYSICAL LAYER DEVICE HAVING INTEGRATED PHYSICAL CODING AND FORWARD ERROR CORRECTION SUB-LAYERS
App. No. 15/336,974
→
IC STRUCTURE INCLUDING TSV HAVING METAL RESISTANT TO HIGH TEMPERATURES AND METHOD OF FORMING SAME
App. No. 15/292,721
→
AMPLIFIER CIRCUIT WITH SINGLE-ENDED INPUT AND DIFFERENTIAL OUTPUTS
App. No. 15/277,344
→
INTEGRATED INTERFACE STRUCTURE
App. No. 15/276,182
→
INTEGRATED LEVEL TRANSLATOR AND LATCH FOR FENCE ARCHITECTURE
App. No. 15/269,139
→
ADDRESS BASED MEMORY DATA PATH PROGRAMMING SCHEME
App. No. 15/266,261
→
IC STRUCTURE ON TWO SIDES OF SUBSTRATE AND METHOD OF FORMING
App. No. 15/239,976
→
SWITCHED CAPACITOR CIRCUIT STRUCTURE WITH METHOD OF CONTROLLING SOURCE-DRAIN RESISTANCE ACROSS SAME
App. No. 15/213,529
→
TAMPER DETECTION FOR A CHIP PACKAGE
App. No. 15/195,029
→
SEMICONDUCTOR DEVICE CONTACT STRUCTURE HAVING STACKED NICKEL, COPPER, AND TIN LAYERS
App. No. 15/191,723
→
ALGORITHMIC N SEARCH/M WRITE TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)
App. No. 15/185,956
→
INTEGRATED CIRCUIT STRUCTURE HAVING THROUGH-SILICON VIA AND METHOD OF FORMING SAME
App. No. 15/176,598
→
SELF PRE-CHARGING MEMORY CIRCUITS
App. No. 15/175,466
→
MATCHLINE PRECHARGE ARCHITECTURE FOR SELF-REFERENCE MATCHLINE SENSING
App. No. 15/164,325
→
NETLIST EDITING OF GRAPHICAL DATA
App. No. 15/142,511
→
DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY
App. No. 15/140,016
→
FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST
App. No. 15/136,404
→
TIMING/POWER RISK OPTIMIZED SELECTIVE VOLTAGE BINNING USING NON-LINEAR VOLTAGE SLOPE
App. No. 15/083,692
→
STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH IMPROVED BOOST
App. No. 15/076,139
→
SENSE AMPLIFIER AND LATCHING SCHEME
App. No. 15/054,553
→
CONVERTING AN XY TCAM TO A VALUE TCAM
App. No. 15/048,256
→
INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION
App. No. 15/048,066
→
MEMORY BUILT-IN SELF-TEST (MBIST) TEST TIME REDUCTION
App. No. 15/019,590
→
THRESHOLD VOLTAGE (VT)-TYPE TRANSISTOR SENSITIVE AND/OR FAN-OUT SENSITIVE SELECTIVE VOLTAGE BINNING
App. No. 15/015,535
→
GIMBAL ASSEMBLY TEST SYSTEM AND METHOD
App. No. 15/014,479
→
METHOD, APPARATUS AND SYSTEM FOR VOLTAGE COMPENSATION IN A SEMICONDUCTOR WAFER
App. No. 15/013,956
→
Application specific integrated circuit (ASIC) test screens and selection of such screens
App. No. 15/012,331
→
VOLTAGE-AWARE ADAPTIVE STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT
App. No. 15/009,132
→
HIGH PERFORMANCE MULTIPLEXED LATCHES
App. No. 15/003,598
→
AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF INTEGRATED CIRCUIT (IC) DESIGN BLOCKS
App. No. 15/002,550
→
ENVIRONMENTALLY AWARE MOBILE COMPUTING DEVICES
App. No. 15/001,763
→
OPERATIONAL AMPLIFIER WITH CURRENT-CONTROLLED UP OR DOWN HYSTERESIS
App. No. 14/992,426
→
CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO REDUCE LATENCY
App. No. 14/990,125
→
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES FOR EFUSES
App. No. 14/971,644
→
SYSTEM AND METHOD TO SPEED UP PLL LOCK TIME ON SUBSEQUENT CALIBRATIONS VIA STORED BAND VALUES
App. No. 14/964,327
→
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
App. No. 14/961,484
→
TEMPERATURE-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS
App. No. 14/945,530
→