Sense-line muxing scheme
The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.
1. A structure comprising a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period,
wherein the self-referenced multiplexer circuit further comprises a self-referenced sense amplifier and at least one multiplexer which opens all multiplexer legs to transfer an input of the self-referenced self amplifier to the plurality of sense lines during the first time period,
the self-referenced sense amplifier comprises a first PMOS transistor and a second PMOS transistor, the first PMOS transistor has a gate connected to a reset signal and a drain connected to a set-reset (SR) latch, and
the SR latch receives the reset signal and outputs a signal to a gate of the second PMOS transistor of the self-referenced sense amplifier.
2. The structure of claim 1 , wherein the self-referenced sense amplifier is configured to self-calibrate by pre-charging the input to the voltage threshold of the self-referenced sense amplifier and transferring the voltage threshold in the input to the plurality of sense lines coupled to the self-referenced sense amplifier during the first time period.
3. The structure of claim 1 , wherein the self-referenced multiplexer circuit further comprises a control block which controls each multiplexer leg of the at least one multiplexer to either open or close.
4. The structure of claim 1 , wherein the at least one multiplexer closes all unselected multiplexer legs and opens a selected multiplexer leg to sense and detect the value of the selected sense line during the second time period.
5. The structure of claim 1 , wherein the at least one multiplexer comprises at least one pass gate which opens all multiplexer legs during the first time period and opens a selected multiplexer leg during the second time period.
6. The structure of claim 1 , wherein the first time period is a pre-charge time period and the second time period is a sense and detect time period.
7. The structure of claim 1 , further comprising a plurality of bit switches which control whether the plurality of sense lines are connected to the self-referenced sense amplifier during the first time period and the second time period.
8. The structure of claim 1 , wherein the voltage threshold is approximately half of a voltage of a power supply which powers the self-referenced multiplexer circuit.
9. A structure comprising a self-referenced multiplexer circuit which comprises a self-referenced sense amplifier configured to self-calibrate by pre-charging an input to a voltage threshold and transfer the input to a plurality of sense lines during a pre-charging time period and at least one multiplexer configured to close all unselected multiplexer legs and open a selected multiplexer leg to sense and detect a value of a selected sense line of the sense lines during a sense and detect time period,
wherein the at least one multiplexer is configured to open all multiplexer legs to transfer the input of the self-referenced sense amplifier to the plurality of sense lines during the pre-charging time period,
the self-referenced sense amplifier comprises a first PMOS transistor and a second PMOS transistor, the first PMOS transistor has a gate connected to a reset signal and a drain connected to a set-reset (SR) latch, and
the SR latch receives the reset signal and outputs a signal to a gate of the second PMOS transistor of the self-referenced sense amplifier.
10. The structure of claim 9 , wherein the self-referenced multiplexer circuit further comprises a control block which controls each multiplexer leg of the at least one multiplexer to either open or close.
11. The structure of claim 9 , wherein the at least one multiplexer comprises at least one pass gate which opens all multiplexer legs during the pre-charging time period and opens a selected multiplexer leg during the sense and detect time period.
12. The structure of claim 9 , wherein the pre-charging time period occurs before the sense and detect time period.
13. The structure of claim 9 , further comprising a plurality of bit switches which control whether the plurality of sense lines are connected to the self-referenced sense amplifier during the pre-charging time period and the sense and detect time period.
14. The structure of claim 9 , wherein the voltage threshold is approximately half of a voltage of a power supply which powers the self-referenced multiplexer circuit.
15. A method, comprising:
pre-charging a plurality of sense lines to a voltage threshold in a first time period;
selecting a sense line of the plurality of sense lines in a second time period; and
sensing and detecting a value of the selected sense line in the second time period,
wherein the pre-charging the plurality of sense lines to the voltage threshold in the first time period comprises opening all multiplexer legs of at least one multiplexer to transfer an input of a self-referenced sense amplifier to the plurality of sense lines during the first time period,
the self-referenced sense amplifier comprises a first PMOS transistor and a second PMOS transistor, the first PMOS transistor has a gate connected to a reset signal and a drain connected to a set-reset (SR) latch, and
the SR latch receives the reset signal and outputs a signal to a gate of the second PMOS transistor of the self-referenced sense amplifier.
16. The method of claim 15 , wherein the sensing and detecting the value of the selected sense line in the second time period comprises closing all unselected multiplexer legs of the at least one multiplexer and opening a selected multiplexer leg to sense and detect the value of the selected sense line during the second time period.
17. The method of claim 15 , wherein the voltage threshold is approximately half of a voltage of a power supply which powers the self-referenced multiplexer circuit.
18. The structure of claim 1 , wherein the self-referenced sense amplifier further comprises an inverter with an input connected to a sense amplifier input and an output of the inverter connected to a gate of a third transistor.
19. The structure of claim 18 , wherein the third transistor is a NMOS transistor which is coupled to a drain of the second PMOS transistor and the sense amplifier input.