Switched capacitor circuit structure with method of controlling source-drain resistance across same

1. A switched capacitor circuit structure comprising:

a switching transistor including a gate terminal, a source terminal, and a drain terminal, wherein the switching transistor further includes:

a fully depleted semiconductor on insulator (FDSOI) channel region positioned laterally between the source terminal and the drain terminal,

a buried insulator layer positioned directly beneath the FDSOI channel region, and

a back gate terminal including n type semiconductor separated from the channel region of the switching transistor by the buried insulator layer;

a biasing node coupled to the back-gate terminal of the switching transistor, the biasing node being alternately selectable between an on state and an off state;

a first capacitor coupled to the source of the switching transistor;

a second capacitor coupled to the drain of the switching transistor; and

a first enabling node coupled to the gate of the switching transistor, the first enabling node being alternately selectable between an on state and an off state.

2. The circuit structure of claim 1 , wherein the biasing node being in the on state lowers a threshold voltage of the gate terminal of the switching transistor.

3. The circuit structure of claim 1 , wherein the biasing node being in the on state lowers a source-drain resistance of the switching transistor, relative to the biasing node being in the off state.

4. The circuit structure of claim 1 , wherein the first and second capacitors comprise portions of a voltage-controlled oscillator circuit or portions of a digitally-controlled oscillator circuit.

5. The circuit structure of claim 1 , further comprising:

a first bypass transistor with a source and drain coupled to opposing terminals of the first capacitor; and

a second bypass transistor with a source and drain coupled to opposing terminals of the second capacitor,

wherein the first bypass transistor includes a gate coupled to a second enabling node, and

wherein the second bypass transistor includes a gate coupled to the second enabling node.

6. The circuit structure of claim 5 , wherein the first enabling node is coupled to the second enabling node through an inverter, such that the first enabling node being in the off state causes the second enabling node to be in an on state, or the first enabling node being in the on state causes the second enabling node to be in an off state.

7. The circuit structure of claim 1 , further comprising:

a first node positioned directly between the first capacitor and the source terminal of the switching transistor, the first node being coupled to the drain of a first node transistor; and

a second node positioned directly between the second capacitor and the drain terminal of the switching transistor, the second node being coupled to the drain of a second node transistor,

wherein the gate of the first node transistor and the gate of the second node transistor are coupled to the first enabling node.

8. A method of controlling source-drain resistance in a switched capacitor circuit, the method comprising:

applying a voltage bias to a biasing node of a circuit structure, the circuit structure including:

a switching transistor, including a gate terminal, a source terminal, and a drain terminal, wherein the switching transistor further includes:

a fully depleted semiconductor on insulator (FDSOI) channel region positioned laterally between the source terminal and the drain terminal,

a buried insulator layer positioned directly beneath the FDSOI channel region, and

a back gate terminal, coupled to the biasing node, including n type semiconductor separated from the channel region of the switching transistor by the buried insulator layer,

a first capacitor coupled to the source of the switching transistor, and

a second capacitor coupled to the drain of the switching transistor;

wherein applying the voltage bias lowers a source-drain resistance between the first and second capacitors across the source and drain terminals of the switching transistor; and

applying an enabling voltage to the gate terminal of the switching transistor, during the applying of the voltage bias to the back-gate terminal of the switching transistor.

9. The method of claim 8 , wherein applying the voltage bias to the back-gate terminal of the switching transistor further lowers a threshold voltage of the gate terminal of the switching transistor relative to the voltage bias not being applied to the back-gate terminal.

10. The method of claim 8 , wherein the circuit structure further includes:

a first bypass transistor including a first gate, the first bypass transistor's source and drain being coupled to opposing terminals of the first capacitor, and

a second bypass transistor including a second gate, the source and drain of the second bypass transistor being coupled to opposing terminals of the second capacitor,

wherein applying the enabling voltage to the gate terminal of the switching transistor further includes applying an inverse of the enabling voltage to the first and second gates of the first and second bypass transistors.

11. The method of claim 10 , wherein the gate terminal of the switching transistor is cross-coupled to the first and second gates of the first and second bypass transistors through an inverter.

12. The method of claim 8 , wherein the first and second capacitors comprise portions of a voltage-controlled oscillator circuit or portions of a digitally-controlled oscillator circuit.

13. The method of claim 8 , wherein the circuit structure further includes:

a first node positioned directly between the first capacitor and the source terminal of the switching transistor, the first node being coupled to the drain of a first node transistor; and

a second node positioned directly between the second capacitor and the drain terminal of the switching transistor, the second node being coupled to the drain terminal of a second node transistor,

wherein the gates of the first node transistor and the second node transistor are coupled to the first enabling node, such that applying the enabling voltage to the gate terminal of the switching transistor switches each of the first node transistor and the second node transistor into an on state.

14. A switched capacitor circuit structure comprising:

a switching transistor including a gate terminal, a source terminal, and a drain terminal, wherein the switching transistor further includes:

a fully depleted semiconductor on insulator (FDSOI) channel region positioned laterally between the source terminal and the drain terminal,

a buried insulator layer positioned directly beneath the FDSOI channel region, and

a back gate terminal including n type semiconductor separated from the channel region of the switching transistor by the buried insulator layer;

a biasing node coupled to the back-gate terminal of the switching transistor, the biasing node being alternately selectable between an on state and an off state;

a first capacitor coupled to the source of the switching transistor at a first node;

a second capacitor coupled to the drain of the switching transistor at a second node;

a first node transistor with the drain thereof coupled to the first node, such that a drain terminal of the first node transistor is directly connected to the first capacitor and the source terminal of the switching transistor;

a second node transistor with the drain thereof coupled to the second node, such that a drain terminal of the second node transistor is directly connected to the second capacitor and the drain terminal of the switching transistor; and

a first enabling node coupled to the gate of the switching transistor, the first node transistor and the second node transistor, the first enabling node being alternately selectable between an on state and an off state.

15. The circuit structure of claim 14 , further comprising:

a first bypass transistor with a source and a drain thereof coupled to opposing terminals of the first capacitor; and

a second bypass transistor with a source and a drain thereof coupled to opposing terminals of the second capacitor,

wherein the gates of the first and second bypass transistors are coupled to a second enabling node.

16. The circuit structure of claim 15 , wherein the first enabling node is coupled to the second enabling node through an inverter, such that the first enabling node being in the off state causes the second enabling node to be in an on state, or the first enabling node being in the on state causes the second enabling node to be in an off state.

17. The circuit structure of claim 14 , wherein the first and second capacitors comprise portions of a voltage-controlled oscillator circuit or portions of a digitally-controlled oscillator circuit.

18. The circuit structure from claim 17 , wherein the biasing node being in the on-state increases a quality factor of the voltage-controlled oscillator circuit or the digitally-controlled oscillator circuit above an initial quality factor with the biasing node in the off-state.