Bit line strapping scheme for high density SRAM
A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.
1. A structure comprising a write bit switch device which comprises a plurality of bit switch devices positioned at different positions in a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.
2. The structure of claim 1 , wherein the plurality of bit switch devices comprise:
a first bit switch device which is positioned at a bit slice of the memory cell array; and
a second bit switch device which is positioned at an array edge of the memory cell array.
3. The structure of claim 1 , further comprising a write driver which is configured to perform the write operations using the strapped bit line on the selected column of the memory cell array, and the strapped bit line being a low resistance, high capacitance bit line configuration.
4. The structure of claim 1 , further comprising a word line driver which is configured to drive a plurality of write bit switch lines for the write bit switch device.
5. The structure of claim 4 , wherein the word line driver is further configured to drive the plurality of write bit switch lines for the write bit switch device using a plurality of inverters.
6. The structure of claim 1 , wherein the write bit switch device is further configured to enable read operations using another non-strapped bit line for fast sensing, and the another non-strapped bit line being a high resistance, low capacitance bit line configuration.
7. The structure of claim 1 , wherein the memory cell array is part of a static random access memory (SRAM).
8. A structure comprising a write bit switch device which includes a first bit switch device and a second bit switch device positioned at different locations in a memory cell array, the write bit switch device being configured to enable write operations at a specified number of cells per bit line using a shared strapped bit line between adjacent columns of the memory cell array in a static random access memory (SRAM).
9. The structure of claim 8 , wherein the first bit switch device is positioned at a bit slice of the memory cell array and the second bit switch device is positioned at an array edge of the memory cell array.
10. The structure of claim 8 , further comprising a write driver which is configured to perform write operations using the shared strapped bit line between adjacent columns at the memory cell array, and the shared strapped bit line being a low resistance, high capacitance bit line configuration.
11. The structure of claim 8 , further comprising a word line driver which is configured to drive a plurality of write bit switch lines for the write bit switch device.
12. The structure of claim 11 , wherein the word line driver is further configured to drive the plurality of write bit switch lines for the write bit switch device using a plurality of inverters.
13. The structure of claim 8 , wherein the write bit switch device is further configured to enable read operations using another non-strapped bit line for fast sensing.
14. The structure of claim 13 , wherein the another non-strapped bit line is a high resistance, low capacitance bit line configuration.
15. The structure of claim 8 , wherein at least one write line is routed from the write bit switch device to the memory cell array.
16. A method, comprising:
setting up at least one write operation for a write bit switch device in a memory cell array using a shared strapped bit line between adjacent columns of the memory cell array; and
performing the at least one write operation at a specified number of cells per bit line at a selected column of the adjacent columns of the memory cell array using the shared strapped bit line after setting up of the at least one write operation for the write bit switch device.
17. The method of claim 16 , further comprising receiving a write bit switch clock before performing the at least one write operation.
18. The method of claim 16 , wherein the write bit switch device comprises a first bit switch device positioned at a bit slice of the memory cell array and a second bit switch device positioned at an array edge of the memory cell array to speed up the at least one write operation.
19. The method of claim 16 , wherein the setting up the at least one write operation for the write bit switch device using the shared strapped bit line of the memory cell array comprises:
setting up a plurality of data lines during a write data setup time; and
precharging the shared strapped bit line of the memory cell array to a specified voltage value based on a power supply voltage.
20. The method of claim 16 , wherein the memory cell array is part of a static random access memory (SRAM).