IP Library Granted Patent US 9,653,330
Granted Patent B1
US 9,653,330 · App. 15/015,535 · Granted May 16, 2017

Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning

Inventors: Jeanne P. Bickford (Essex Junction, VT); John R. Goss (Saint Albans, VT); Robert J. McMahon (Essex Junction, VT); Troy J. Perry (Georgia, VT); Thomas G. Sopchak (Williston, VT)
Assignee: GLOBALFOUNDRIES INC.
H01L21/67271G01R31/31718G06F17/5045H01L22/14
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,653,330
App. No.
15/015,535
Granted
May 16, 2017
Kind
B1
Abstract

Disclosed are methods for performing threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning (SVB) to improve SVB accuracy and, thereby product yield and reliability. In the methods, a process distribution for an integrated circuit chip design is divided into process windows, each associated with a corresponding performance range and a corresponding minimum supply voltage. First performance measurements are acquired from first performance monitors associated with first transistors on chips manufactured according to the design. Based on the first performance measurements, the chips are assigned to groups corresponding to the process windows. Second performance measurements are also be acquired from second performance monitors associated with second transistors, which are on the chips and which have either a different VT-type or a different maximum fan-out than the first transistors. Based on the second performance measurements, a determination is made as to whether chip group reassignment is warranted.

Claims (56)

1. A method comprising:

dividing a process distribution for an integrated circuit chip design into process windows, each process window being associated with a corresponding performance range and a corresponding minimum supply voltage;

manufacturing chips according to the design, each chip comprising at least first transistors having a first threshold voltage type and second transistors having a second threshold voltage-type;

testing the chips to acquire first performance measurements from first performance monitors associated with the first transistors and second performance measurements from second performance monitors associated with the second transistors;

based on the first performance measurements, assigning the chips to groups corresponding to the process windows; and,

based on the second performance measurements, determining whether chip group reassignment is warranted.

2. The method of claim 1 , the determining of whether chip group reassignment is warranted comprising:

selecting a specific chip assigned to a first group, which corresponds to a first process window associated with a first performance range and a first minimum supply voltage;

determining whether a second performance measurement, which is acquired from a second performance monitor associated with a second transistor on the specific chip, is slower than a slowest performance measurement indicated by the first performance range; and,

reassigning the specific chip to a second group, which corresponds to a second process window associated with a second performance range and a second minimum supply voltage that is higher than the first minimum supply voltage, when the second performance measurement is slower than the slowest performance measurement indicated by the first performance range.

3. The method of claim 1 , further comprising defining the process distribution using a specific supply voltage and at a specific operating temperature.

4. The method of claim 3 , the testing being performed using the specific supply voltage and at the specific operating temperature.

5. The method of claim 4 ,

performing additional testing of the chips to acquire additional first performance measurements from the first performance monitors and additional second performance measurements from the second performance monitors, the additional testing being performed using a different supply voltage than the specific supply voltage; and,

based on the additional first performance measurements and the additional second performance measurements, determining whether additional chip group reassignment is warranted.

6. The method of claim 4 , further comprising:

performing additional testing of the chips to acquire additional first performance measurements from the first performance monitors and additional second performance measurements from the second performance monitors, the additional testing being performed at a different operating temperature than the specific operating temperature; and,

based on the additional first performance measurements and the additional second performance measurements, determining whether additional chip group reassignment is warranted.

7. The method of claim 1 , the determining of whether chip group reassignment is warranted further being based on leakage power measurements, given leakage power ranges associated with the process windows.

8. A method comprising:

dividing a process distribution for an integrated circuit chip design into process windows, each process window being associated with a corresponding performance range and a corresponding minimum supply voltage;

manufacturing chips according to the design, each chip comprising at least first transistors having a specific threshold voltage type and a first maximum fan-out and second transistors having the specific threshold voltage-type and a second maximum fan-out;

testing the chips to acquire first performance measurements from first performance monitors associated with the first transistors and second performance measurements from second performance monitors associated with the second transistors;

based on the first performance measurements, assigning the chips to groups corresponding to the process windows; and,

based on the second performance measurements, determining whether chip group reassignment is warranted.

9. The method of claim 8 , the determining of whether chip group reassignment is warranted comprising:

selecting a specific chip assigned to a first group, which corresponds to a first process window associated with a first performance range and a first minimum supply voltage;

determining whether a second performance measurement, which is acquired from a second performance monitor associated with a second transistor on the specific chip, is slower than a slowest performance measurement indicated by the first performance range; and,

reassigning the specific chip to a second group, which corresponds to a second process window associated with a second performance range and a second minimum supply voltage that is higher than the first minimum supply voltage, when the second performance measurement is slower than the slowest performance measurement indicated by the first performance range.

10. The method of claim 8 , further comprising defining the process distribution using a specific supply voltage and at a specific operating temperature.

11. The method of claim 10 , the testing being performed using the specific supply voltage and at the specific operating temperature.

12. The method of claim 11 , further comprising:

performing additional testing of the chips to acquire additional first performance measurements from the first performance monitors and additional second performance measurements from the second performance monitors, the additional testing being performed using a different supply voltage than the specific supply voltage; and,

based on the additional first performance measurements and the additional second performance measurements, determining whether additional chip group reassignment is warranted.

13. The method of claim 11 , further comprising:

performing additional testing of the chips to acquire additional first performance measurements from the first performance monitors and additional second performance measurements from the second performance monitors, the additional testing being performed at a different operating temperature than the specific operating temperature; and,

based on the additional first performance measurements and the additional second performance measurements, determining whether additional chip group reassignment is warranted.

14. The method of claim 8 , the determining of whether chip group reassignment is warranted further being based on leakage power measurements, given leakage power ranges associated with the process windows.

15. A method comprising:

dividing a process distribution for an integrated circuit chip design into process windows, each process window being associated with a corresponding performance range and a corresponding minimum supply voltage;

manufacturing chips according to the design, each chip comprising at least first transistors having a first threshold voltage type and a first maximum fan-out, second transistors having the first threshold voltage type and a second maximum fan-out, third transistors having a second threshold voltage type and a third maximum fan-out and fourth transistors having the second threshold voltage type and a fourth maximum fan-out;

testing the chips to acquire first performance measurements from first performance monitors associated with the first transistors, second performance measurements from second performance monitors associated with the second transistors, third performance measurements from third performance monitors associated with the third transistors, and fourth performance measurements from fourth performance monitors associated with the fourth transistors;

based on the first performance measurements, assigning the chips to groups corresponding to the process windows; and

based on any of the second performance measurements, the third performance measurements and the fourth performance measurements, determining whether chip group reassignment is warranted.

16. The method of claim 15 , the determining of whether chip group reassignment is warranted comprising:

selecting a specific chip assigned to a first group, which corresponds to a first process window associated with a first performance range and a first minimum supply voltage;

determining whether, for the specific chip, any of a second performance measurement, a third performance measurement or a fourth performance measurement, is slower than a slowest performance measurement indicated by the first performance range; and,

reassigning the specific chip to a second group, which corresponds to a second process window associated with a second performance range and a second minimum supply voltage that is higher than the first minimum supply voltage, when the second performance measurement, the third performance measurement or the fourth performance measurement is slower than the slowest performance measurement indicated by the first performance range.

17. The method of claim 15 , further comprising defining the process distribution using a specific supply voltage and at a specific operating temperature.

18. The method of claim 17 , the testing being performed using the specific supply voltage and at the specific operating temperature.

19. The method of claim 18 , further comprising:

performing additional testing of the chips to acquire additional first performance measurements from the first performance monitors, additional second performance measurements from the second performance monitors, additional third performance measurements from the third performance monitors and additional fourth performance measurements from the fourth performance monitors, the additional testing being performed using a different supply voltage than the specific supply voltage; and,

based on the additional first performance measurements, the additional second performance measurements, the additional third performance measurements and the additional fourth performance measurements, determining whether additional chip group reassignment is warranted.

20. The method of claim 18 , further comprising:

performing additional testing to acquire additional first performance measurements from the first performance monitors, additional second performance measurements from the second performance monitors, additional third performance measurements from the third performance monitors and additional fourth performance measurements from the fourth performance monitors, the additional first performance measurements, the additional testing being performed at a different operating temperature than the specific operating temperature; and,

based on the additional first performance measurements, the additional second performance measurements, the additional third performance measurements and the additional fourth performance measurements, determining whether additional chip group reassignment is warranted.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2019
From: GLOBALFOUNDRIES U.S. INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051070/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2019
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 050122/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: BICKFORD, JEANNE P.; GOSS, JOHN R.; MCMAHON, ROBERT J.; PERRY, TROY J.; SOPCHAK, THOMAS G.
To: GLOBALFOUNDRIES INC.
Reel/Frame 037666/0274 →