Digital frequency multiplier to generate a local oscillator signal in FDSOI technology

1. A transformer-less digital frequency multiplier (DFM) device comprising:

an input receiving a RF_IN signal and a RF_OUT out signal that is an integer multiple of the RF_IN signal;

an edge detector that provides a quantized or a state output comparing the RF_IN signal and a RF_FB signal that determines if the RF_FB signal is ahead or delayed to the RF_IN signal;

a statemachine that has counters and decimation circuits to provide a digitized output to a set of digital to analog converters (DACs) that tunes delays between the RF_IN and the RF_OUT signals;

a digital delay-locked loop (DLL) for generating delay signals from the RF_IN signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a RF_IN multiplied output signal as a second RF_OUT signal;

a first DAC of the set of DACs that takes a digital word from the statemachine and provide an analog control to a supply circuit of the DLL to adjust a delay through a supply voltage; and

a second DAC of the set of DACs that takes a digital word from the statemachine and provide analog control to a backgate circuit of the DLL to adjust the delay though a backgate voltage.

2. The DFM device of claim 1 , further comprising a Wi-Fi transmitter/receiver.

3. The DFM device of claim 1 , wherein varying the supply voltage changes an output time delay of an at least one delay cell in the DLL to synchronize the RF_OUT signal and the RF_IN signal.

4. The DFM device of claim 1 , wherein an output time delay of the DLL is also a function of the backgate voltage.

5. The DFM device of claim 4 , wherein varying the backgate voltage also changes an output time delay of an at least one delay cell in DLL to synchronize RF_OUT signal and the RF_IN signal.

6. The DFM device of claim 1 , wherein the statemachine further processes an output of the edge detector to provide a set of quantized outputs that drive the first DAC and the second DAC.

7. The DFM device of claim 1 , further comprised of statemachine that comprises a series of counters and a series decimation circuits in order to provide a set of quantized outputs that drive the first DAC and the second DAC.

8. The DFM device of claim 1 , wherein the DFM device is implemented using Fully-Depleted Silicon-On-Insulator (FD-SOI) technology using a backgate.

9. The DFM device of claim 1 , wherein the DFM device is implemented using Partially-Depleted Silicon-On-Insulator (PD-SOI) technology that has a device with a bulk layer.

10. A method to perform low power scalable local oscillator frequency generation using digital frequency multiplication, comprising:

receiving a RF_IN signal and a RF_FB signal at an edge detector;

generating a quantized output that determines whether the RF_FB signal is ahead or delayed to the RF_IN signal;

generating a first set of delay signals with a digital delay-locked loop (DLL) that produces a set of different phases from the RF_IN signal as inputs for an edge combiner wherein the edge combiner takes in different phases from the digital DLL and produces an integer multiplied output of RF_IN signal called a RF_OUT signal; and

an output time delay of the digital DLL is a function of a supply voltage and a backgate voltage, and wherein varying the supply voltage or backgate voltage changes the output time delay of a set of DLL signals.

11. The method of claim 10 , wherein varying the backgate voltage also changes an output time delay of the RF_IN signal to generate set of multiple phases for the edge combiner.

12. The method of claim 10 , further comprised of adjusting a voltage of the RF_IN signal and a voltage of the RF_OUT signal.

13. The method of claim 10 , further comprising an application in a Wi-Fi transmitter/receiver.

14. The method of claim 10 , wherein the method is implemented using Fully-Depleted Silicon-On-Insulator (FD-SOI) technology.

15. A transceiver system for using a digital frequency multiplier (DFM) device to generate an integer multiplied signal comprising;

an input receiving a RF_IN signal and a RF_FB signal that is an integer multiple of the RF_IN signal;

an edge detector that provides a quantized output comparing the RF_IN signal and the RF_FB signal;

a statemachine that has a plurality of counters and a plurality of decimation circuits that receives an output of the edge detector to provide a digitized output signal to a digital to analog converter (DAC) that tunes a set of delays between the RF_IN and the RF_FB signals through supply and backgate circuits;

a digital delay-locked loop (DLL) for generating delay signals from the RF_IN signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a RF_IN multiplied output signal as a second RF_OUT signal; and

a DAC that takes a digital word from the statemachine and provide an analog control to a supply circuit of the DLL to adjust delay through a supply voltage and a backgate voltage.

16. The system of claim 15 , further comprising a Wi-Fi transmitter/receiver.

17. The system of claim 15 , wherein the DFM device is implemented using Fully-Depleted Silicon-On-Insulator (FD-SOI) technology.

18. The system of claim 15 , wherein the DFM device is implemented using Partially-Depleted Silicon-On-Insulator (PD-SOI) technology.