Static random access memory (SRAM) write assist circuit with improved boost
Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.
1. A write assist circuit, comprising:
a boost capacitor with a first node coupled to a boost signal and a second node connected to a field effect transistor (FET) diode stack;
a plurality of boost enabled transistors which each contain a gate connected to a boost control signal; and
a controlled current source coupled between a ground signal and the second node of the boost capacitor,
wherein the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.
2. The write assist circuit of claim 1 , wherein the boost capacitor has a charging path to the power supply signal.
3. The write assist circuit of claim 1 , wherein the discharge path comprises the plurality of boost enabled transistors and a plurality of write mask transistors to allow selection of the boost signal to be boosted.
4. The write assist circuit of claim 1 , wherein the FET diode stack comprises:
a first n-type FET (NFET) transistor with a drain connected to the power supply signal, a gate connected to the power supply signal, and a source connected to a drain of a second NFET transistor;
the second NFET transistor with the drain of the second NFET transistor connected to the source of the first NFET transistor, a gate connected to the power supply signal, and a source connected to the second node of the boost capacitor.
5. The write assist circuit of claim 1 , wherein the controlled current source is part of a current mirror.
6. The write assist circuit of claim 5 , wherein the current mirror comprises a plurality of reference diodes which can be enabled or disabled by a digital control to adjust a controlled current level of the controlled current source.
7. The write assist circuit of claim 1 , wherein the write assist circuit is a static random access memory (SRAM) write assist circuit.
8. The write assist circuit of claim 1 , wherein the boost capacitor is an NFET transistor.
9. The write assist circuit of claim 1 , wherein discharge of the second node of the boost capacitor is limited to an FET threshold plus overdrive.