Testing monolithic three dimensional integrated circuits
Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.
1. A structure, comprising:
a first functional layer comprising first test scan chains;
a first inter-layer dielectric (ILD) layer on the first functional layer;
a test layer on the first ILD layer;
a second ILD layer on the test layer;
a second functional layer on the second ILD layer, the second functional layer comprising second test scan chains;
a third ILD layer on the second functional layer and having connections to a testing module, the test layer comprising:
an interface register controlling signals from the testing module to one of the first test scan chains and the second test scan chains, and
an instruction register connected to the interface register, the instruction register processing testing instructions from the testing module, wherein the interface register and the instruction register are located in the test layer between the first functional layer and the second functional layer; and
inter-layer vias connecting the testing module to each of (i) the first test scan chains of the first functional layer; and (ii) the second test scan chains of the second functional layer through the interface register of the test layer and the first, second, and third ILD layers.
2. The structure according to claim 1 , the instruction register processing testing instructions from the testing module and selecting a test data register to be active between test data in (TDI) and test data out (TDO).
3. The structure according to claim 1 , the test layer further comprising:
a test access point (TAP) controller connected to the interface register and the instruction register.
4. The structure according to claim 3 , the TAP controller being programmable to control the flow of data bits to the instruction register.
5. The structure according to claim 3 , the test layer further comprising:
a first multiplexer having data inputs and control inputs comprising a data input from the interface register and a control input from the instruction register.
6. The structure according to claim 5 , the test layer further comprising:
a second multiplexer having data inputs and control inputs comprising a first data input from the instruction register and a second data input from an output of the first multiplexer and a control input from the TAP controller.
7. The structure according to claim 3 , the test layer further comprising:
a configuration register to determine the configuration for the TAP controller.
8. The structure according to claim 1 , the test layer further comprising:
a bypass register.
9. The structure according to claim 1 , each of the first functional layer and the second functional layer further comprising:
functional components of an integrated circuit, the test scan chains being connected to the functional components;
test data CoDeCs; and
test access mechanisms.
10. The structure according to claim 1 , each of the first test scan chains and the second test scan chains having input and output connections to the testing module.
11. A structure, comprising:
a first functional layer having a top surface and a bottom surface, the first functional layer comprising:
first functional components of an integrated circuit (IC), and
first test scan chains connected to the first functional components, the first test scan chains having first input and output connections;
a first inter-layer dielectric (ILD) layer having a top surface and a bottom surface, the bottom surface of the first ILD layer being connected to the top surface of the first functional layer;
a test layer having a top surface and a bottom surface, the bottom surface of the test layer being connected to the top surface of the first ILD layer;
a second ILD layer having a top surface and a bottom surface, the bottom surface of the second ILD layer being connected to the top surface of the test layer;
a second functional layer having a top surface and a bottom surface, the bottom surface of the second functional layer being connected to the top surface of the second ILD layer, the second functional layer comprising:
second functional components of the IC, and
second test scan chains connected to the second functional components, the second test scan chains having second input and output connections;
a third ILD layer having a top surface and a bottom surface, the bottom surface of the third ILD layer being connected to the top surface of the second functional layer and having connections to a testing module,
the test layer comprising:
an interface register controlling signals from the testing module to one of the first test scan chains and the second test scan chains,
an instruction register connected to the interface register, the instruction register processing testing instructions from the testing module,
a test access point (TAP) controller connected to the interface register and the instruction register,
a first multiplexer having data inputs and control inputs comprising a data input from the interface register and a control input from the instruction register, and
a second multiplexer having data inputs and control inputs comprising a first data input from the instruction register and a second data input from an output of the first multiplexer and a control input from the TAP controller; and
inter-layer vias connecting the testing module to the first test scan chains and the second test scan chains through the interface register of the test layer.
12. The structure according to claim 11 , the instruction register processing testing instructions from the testing module and selecting a test data register to be active between test data in (TDI) and test data out (TDO).
13. The structure according to claim 11 , the TAP controller being programmable to control the flow of data bits to the instruction register.
14. The structure according to claim 11 , the test layer further comprising:
a configuration register to determine the configuration for the TAP controller.
15. The structure according to claim 11 , the test layer further comprising:
a bypass register.
16. The structure according to claim 11 , each of the first functional layer and the second functional layer further comprising:
test data CoDeCs; and
test access mechanisms.
17. A method comprising:
receiving a stacked integrated circuit (IC) chip, comprising:
a first functional layer comprising:
first functional components of the IC, and
first test scan chains connected to the first functional components, the first test scan chains having first input and output connections to a testing module;
a second functional layer comprising:
second functional components of the IC, and
second test scan chains connected to the second functional components, the second test scan chains having second input and output connections to the testing module;
a test layer between the first functional layer and the second functional layer, the test layer comprising:
an interface register connected to the first test scan chains and the second test scan chains,
an instruction register connected to the interface register,
a test access point (TAP) controller connected to the interface register and the instruction register,
inter-layer vias connecting the testing module to the first test scan chains and the second test scan chains through the interface register of the test layer,
selecting one of the first test scan chains and the second test scan chains for testing using the interface register;
processing testing instructions from the testing module to the one of the first test scan chains and the second test scan chains using the instruction register; and
controlling the flow of test data using the TAP controller connected to the interface register and the instruction register.
18. The method according to claim 17 , wherein the testing instructions generate test patterns for detecting faults in one of the first functional layer and the second functional layer according to associated test chains.
19. The method according to claim 17 , wherein the instruction register processes testing instructions from the testing module and selects a test data register to be active between test data in (TDI) and test data out (TDO).
20. The method according to claim 17 , further comprising:
bypassing the interface register to apply testing to both the first functional layer and the second functional layer, applying fault testing to each functional layer of the IC.