Feedback circuit at word line ends

1. A device comprising:

an array of memory cells arranged in rows and columns that are perpendicular to each other;

wordlines comprising conductors connected to the memory cells, each of the wordlines is connected to a distinct row of the array of the memory cells;

a wordline driver circuit connected to a near end of the wordlines, the wordline driver circuit outputs an internal clock signal and a wordline select signal; and

a feedback circuit connected to a far end of each of the wordlines, opposite the near end of the wordlines,

the feedback circuit comprises:

an inverter connected to the far end of the wordlines;

an inner positive polarity transistor gated by output from the inverter and electrically connecting the inverter back to the far end of the wordlines to form a first feedback loop;

an outer positive polarity transistor gated by the internal clock signal and electrically connecting a relatively lower voltage source to the inner positive polarity transistor;

an inner negative polarity transistor gated by output from the inverter and electrically connecting the inverter back to the far end of the wordlines to form a second feedback loop; and

an outer negative polarity transistor gated by the internal clock signal and electrically connecting a relatively higher voltage source to the inner negative polarity transistor.

2. The device according to claim 1 , the internal clock signal arrives to the outer positive polarity transistor and the outer negative polarity transistor before the wordline select signal arrives at the far end of the wordlines.

3. The device according to claim 1 , the internal clock signal controls the outer positive polarity transistor and the outer negative polarity transistor before the wordline select signal controls the inner positive polarity transistor and the inner negative polarity transistor.

4. The device according to claim 1 , the inner positive polarity transistor electrically disconnects the relatively lower voltage source from the first feedback loop when the wordline select signal is present, and

the inner negative polarity transistor electrically disconnects the relatively higher voltage source from the second feedback loop when the wordline select signal is not present.

5. The device according to claim 1 , the first feedback loop lowers the voltage of the far end of the wordlines that do not have the wordline select signal by connecting the far end of the wordlines to the relatively lower voltage source, and

the second feedback loop raises the voltage of the far end of one of the wordlines that has the wordline select signal by supplying voltage from the relatively higher voltage source.

6. The device according to claim 1 , the wordlines comprise uninterrupted conductors from the near end to the far end.

7. The device according to claim 1 , the wordlines have a length between the near end and the far end that equals a full length of the rows of the memory cells.

8. A device comprising:

an array of memory cells arranged in rows and columns that are perpendicular to each other;

wordlines comprising conductors connected to the memory cells, each of the wordlines is connected to a distinct row of the array of the memory cells;

bitlines comprising conductors connected to the memory cells, each of the bitlines is connected to a distinct column of the array of the memory cells;

a wordline driver circuit connected to a near end of the wordlines, the wordline driver circuit includes:

a global controller outputting an internal clock signal; and

a decoder outputting a wordline select signal in response to the internal clock signal; and

a feedback circuit connected to a far end of each of the wordlines, opposite the near end of the wordlines,

the feedback circuit comprises:

an inverter connected to the far end of the wordlines;

an inner positive polarity transistor gated by output from the inverter and electrically connecting the inverter back to the far end of the wordlines to form a first feedback loop;

an outer positive polarity transistor gated by the internal clock signal and electrically connecting a relatively lower voltage source to the inner positive polarity transistor;

an inner negative polarity transistor gated by output from the inverter and electrically connecting the inverter back to the far end of the wordlines to form a second feedback loop; and

an outer negative polarity transistor gated by the internal clock signal and electrically connecting a relatively higher voltage source to the inner negative polarity transistor.

9. The device according to claim 8 , the internal clock signal arrives to the outer positive polarity transistor and the outer negative polarity transistor before the wordline select signal arrives at the far end of the wordlines.

10. The device according to claim 8 , the internal clock signal controls the outer positive polarity transistor and the outer negative polarity transistor before the wordline select signal controls the inner positive polarity transistor and the inner negative polarity transistor.

11. The device according to claim 8 , the inner positive polarity transistor electrically disconnects the relatively lower voltage source from the first feedback loop when the wordline select signal is present, and

the inner negative polarity transistor electrically disconnects the relatively higher voltage source from the second feedback loop when the wordline select signal is not present.

12. The device according to claim 8 , the first feedback loop lowers the voltage of the far end of the wordlines that do not have the wordline select signal by connecting the far end of the wordlines to the relatively lower voltage source, and

the second feedback loop raises the voltage of the far end of one of the wordlines that has the wordline select signal by supplying voltage from the relatively higher voltage source.

13. The device according to claim 8 , the wordlines comprise uninterrupted conductors from the near end to the far end.