Sense amplifier latch circuit and sense amplifier multiplexed latch circuit
Embodiments of the present disclosure provide a circuit structure including: a circuit driven by first and second sense amplifier (SA) output; a first driver having a first PMOS coupled to a node and to a pair of serially coupled NMOSs, wherein the first SA output is coupled to the first PMOS and the first NMOS of the first driver; a second driver having a second PMOS coupled to a node and a pair of coupled NMOSs, wherein the second SA output is coupled to the second PMOS and second NMOS of the second driver; a first and second supply PMOS, wherein first supply PMOS is coupled to the node of the first driver and to the second supply PMOS and first NMOS of the second driver, and wherein the second supply PMOS is coupled to node of second driver and to the first supply PMOS and second NMOS of first driver.
1. A sense amplifier latch circuit comprising:
a latch circuit driven by a first and second sense amplifier output;
a first latch driver having a first PMOS transistor coupled to a latch node and to a pair of serially coupled NMOS transistors, wherein the first sense amplifier output is gate coupled to the first PMOS transistor and the first NMOS transistor of the first latch driver;
a second latch driver having a second PMOS transistor coupled to a latch node and to a pair of serially coupled NMOS transistors, wherein the second sense amplifier output is gate coupled to the second PMOS transistor and the second NMOS transistor of the second latch driver;
a first and second supply PMOS transistor, wherein an output of the first supply PMOS transistor is coupled to the latch node of the first latch driver and to a gate of both the second supply PMOS transistor and first NMOS transistor of the second latch driver, and wherein an output of the second supply PMOS transistor is coupled to the latch node of the second latch driver and to a gate of both the first supply PMOS transistor and second NMOS transistor of the first latch driver.
2. The sense amplifier latch circuit of claim 1 , wherein an output of a first gated latch is coupled to the first and second PMOS transistor.
3. The sense amplifier latch circuit of claim 2 , wherein the first gated latch is gated to a first input signal and connected to a first voltage source.
4. The sense amplifier latch circuit of claim 1 , wherein the sense amplifier further comprises a first set of initial inputs.
5. The sense amplifier latch circuit of claim 1 , wherein the sense amplifier further comprises a sensing gated transistor having a first sense enabled input signal.
6. The sense amplifier latch circuit of claim 1 , further comprising an output node coupled to the latch node of the second latch driver.
7. A sense amplifier latch circuit comprising:
a latch circuit driven by a first and a second sense amplifier outputs;
a first latch driver having a first PMOS transistor coupled to a latch node and to at least three serially coupled NMOS transistors, wherein the first sense amplifier output is gate coupled to the first PMOS transistor and the third NMOS transistor of the first latch driver;
a second latch driver having a second PMOS transistor coupled to a latch node and to at least three serially coupled NMOS transistors, wherein the second sense amplifier output is gate coupled to the second PMOS and the third NMOS transistor of the second latch driver;
a first and second supply PMOS transistor, wherein an output of the first supply PMOS transistor is coupled to the latch node of the first latch driver and to a gate of both the second supply PMOS transistor and the first NMOS transistor of the second latch driver, and wherein an output of the second supply PMOS transistor is coupled to the latch node of the second latch driver and to a gate of both the first supply PMOS transistor and the first NMOS transistor.
8. The sense amplifier latch circuit of claim 7 , wherein an output of a first gated latch is coupled to the first and second PMOS transistor.
9. The sense amplifier latch circuit of claim 8 , wherein the first gated latch is gated to a first input signal and connected to a first voltage source.
10. The sense amplifier latch circuit of claim 7 , wherein the sense amplifier further comprises a first set of initial inputs.
11. The sense amplifier latch circuit of claim 7 , wherein the sense amplifier further comprises a sensing gated transistor having a first sense enabled input signal.
12. The sense amplifier latch circuit of claim 7 , further comprising an output node coupled to the latch node of the second latch driver.
13. The sense amplifier latch circuit of claim 7 , wherein each of the first and second supply PMOS transistors are connected to a second and third voltage source respectively.
14. The sense amplifier latch circuit of claim 7 , wherein each of the second NMOS transistors of the first and second latch drivers are gated to an input signal.
15. The sense amplifier latch circuit of claim 14 , wherein the input signal of first and second latch drivers is the same input signal.
16. A sense amplifier multiplexed latch circuit comprising:
a first latch circuit driven by a first and a second sense amplifier outputs;
a first latch driver having a first PMOS transistor coupled to a latch node and to at least three serially coupled NMOS transistors, wherein the first sense amplifier output is gate coupled to the first PMOS transistor and the third NMOS transistor of the first latch driver;
a second latch driver having a second PMOS transistor coupled to a latch node and to at least three serially coupled NMOS transistors, wherein the second sense amplifier output is gate coupled to the second PMOS and the third NMOS transistor of the second latch driver;
a first and second supply PMOS transistor, wherein an output of the first supply PMOS transistor is coupled to the latch node of the first latch driver and to a gate of both the second supply PMOS transistor and the first NMOS transistor of the second latch driver, and wherein an output of the second supply PMOS transistor is coupled to the latch node of the second latch driver and to a gate of both the first supply PMOS transistor and the first NMOS transistor;
a second latch circuit driven by a third and fourth sense amplifier outputs, wherein each of the third and fourth outputs are gate coupled to a control PMOS transistor and a first NMOS transistor of a set of serially coupled NMOS transistors, wherein each of the second NMOS transistors, of the set of serially coupled NMOS transistors, are coupled to an output of the second NMOS transistor of the first and second latch, and wherein the control PMOS transistors, gated to the third and fourth outputs, are coupled to the latch nodes of the first and second latch.
17. The sense amplifier latch circuit of claim 16 , wherein each of the second NMOS transistors of the first and second latch drivers are gated to a first input data signal.
18. The sense amplifier multiplexed latch circuit of claim 16 , wherein each of the second NMOS transistors of the set of serially connected NMOS transistors of the second latch circuit are gated to a second input data signal.
19. The sense amplifier multiplexed latch circuit of claim 16 , wherein an output of a first gated latch is coupled to the first and second control PMOS transistors.
20. The sense amplifier multiplexed latch circuit of claim 16 , wherein an output of a second gated latch is coupled to the control PMOS transistors of the second latch circuit.