IP Library › Granted Patent US 6,127,866
Granted Patent Utility
US 6,127,866 · App. 09/239,487

Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays

Inventors: Albert M. Chu, John A. Fifield, Jason Rotella, Jean-Marc Dortu
Patented Case View Patent ↗
Granted: Oct 3, 2000 Filed: Jan 28, 1999
Inventors
Albert M. Chu
John A. Fifield
Jason Rotella
Jean-Marc Dortu
Assignees (at issue)
Infineon Technologies North America Corp.
International Business Machines Corporation

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Quick Facts
Patent No.
US 6,127,866
App. No.
09/239,487
Filed
1999-01-28
Granted
2000-10-03
Kind
A