Integrated circuit including silicide region to inhibit parasitic currents
View Patent ↗An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.
1. An integrated circuit comprising:
a first diode;
a second diode; and
a semiconductor line directly coupled to the first diode and the second diode, the line comprising a first silicide region between the first diode and the second diode.
2. The integrated circuit of claim 1 , wherein the first silicide region is configured to inhibit minority carriers from coupling between the first diode and the second diode.
3. The integrated circuit of claim 1 , wherein the first silicide, region is configured to inhibit parasitic currents between the first diode and the second diode.
4. The integrated circuit of claim 1 , further comprising:
a first memory element coupled to the first diode; and
a second memory element coupled to the second diode.
5. The integrated circuit of claim 4 , wherein the first memory element comprises a first resistive memory element, and
wherein the second memory element comprises a second resistive memory element.
6. The integrated circuit of claim 4 , wherein the first memory element comprises a first phase change element, and
wherein the second memory element comprises a second phase change element.
7. An integrated circuit comprising:
a first diode;
a second diode; and
a semiconductor line coupled to the first diode and the second diode, the line comprising a first silicide region between the first diode and the second diode,
wherein the line comprises a second silicide region extending perpendicular to the first silicide region.
8. The integrated circuit of claim 7 , wherein the first silicide region is configured to inhibit minority carriers from coupling between the first diode and the second diode.
9. The integrated circuit of claim 7 , wherein the first silicide region is configured to inhibit parasitic currents between the first diode and the second diode.
10. The integrated circuit of claim 7 , further comprising:
a first memory element coupled to the first diode; and
a second memory element coupled to the second diode.
11. The integrated circuit of claim 10 , wherein the first memory element comprises a first resistive memory element, and
wherein the second memory element comprises a second resistive memory element.
12. The integrated circuit of claim 10 , wherein the first memory element comprises a first phase change element, and
wherein the second memory element comprises a second phase change element.
13. A memory comprising:
a first diode;
a second diode;
a line formed in a substrate, the line directly coupled to the first diode and the second diode; and
means for inhibiting minority carriers from coupling within the line between the first diode and the second diode without increasing a resistivity of the line.
14. The memory of claim 13 , further comprising:
a first resistive memory element coupled to the first diode; and
a second resistive memory element coupled to the second diode.
15. The memory of claim 14 , wherein the first resistive memory element comprises a first phase change element, and
wherein the second resistive memory element comprises a second phase change element.
16. The memory of claim 13 , wherein the line comprises a silicide region extending perpendicular to the means for inhibiting minority carriers.
17. A system comprising:
a host; and
a memory device communicatively coupled to the host, the memory device comprising:
a first diode;
a second diode; and
a semiconductor line directly coupled to the first diode and the second diode, the semiconductor line comprising a recombination center in a current path between the first diode and the second diode.
18. The system of claim 17 , wherein the silicide region extends partially through the semiconductor line.
19. The system of claim 17 , wherein the recombination center comprises a silicide region.
20. The system of claim 19 , wherein the semiconductor line comprises a further silicide region extending perpendicular to the silicide region.
21. The system of claim 17 , wherein the memory device further comprises:
a first resistive memory element coupled to the first diode; and
a second resistive memory element coupled to the second diode.
22. The system of claim 21 , wherein the memory device further comprises:
a first bit line coupled to the first resistive memory element; and
a second bit line coupled to the second resistive memory element,
wherein the semiconductor line comprises a word line.
23. The system of claim 22 , wherein the memory device further comprises:
a write circuit configured to program the first resistive memory element and the second resistive memory element;
a sense circuit configured to read the first resistive memory element and the second resistive memory element; and
a controller configured to control the write circuit and the sense circuit.
24. The system of claim 21 , wherein the first resistive memory element comprises a first phase change element, and
wherein the second resistive memory element comprises a second phase change element.