IP Library › Assignment 023963/0502
Patent Assignment
Reel/Frame 023963/0502

Assignment of Assignor's Interest

Recorded: 2010-02-22 Pages: 390
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81739, GERMANY
Covered Properties (159)
Etch Profile Shaping Through Wafer Temperature Control
Patent: 5,605,600 →
Application: 08/402,378 →
Fuse Element for Effective Laser Blow in an Integrated Circuit Device
Patent: 5,608,257 →
Application: 08/477,060 →
Planarized Final Passivation for Semiconductor Devices
Patent: 6,376,911 →
Application: 08/518,209 →
In-Situ Wafer Temperature Control Apparatus for Single Wafer Tools
Patent: 5,667,622 →
Application: 08/519,373 →
Off-State Gate-Oxide Field Reduction in Cmos
Patent: 5,602,410 →
Application: 08/519,669 →
Application of Thin Crystalline SI3N4 Liners in Shallow Trench Isolation (Sti) Structures
Patent: 5,643,823 →
Application: 08/531,844 →
Enhanced Deep Trench Storage Node Capacitance for Dram
Patent: 5,592,412 →
Application: 08/539,475 →
Integrated Polysilicon Diode Contact for Gain Memory Cells
Patent: 5,710,448 →
Application: 08/549,885 →
In-Situ Temperature Measurement Using X-Ray Diffraction
Patent: 5,636,258 →
Application: 08/554,209 →
Method for Forming Semiconductor Structure Using Modulation Doped Silicat Glasses
Patent: 5,770,469 →
Application: 08/578,165 →
Buried-Strap Formation in a Dram Trench Capacitor
Patent: 5,827,765 →
Application: 08/605,622 →
Nitride Cap Formation in a Dram Trench Capacitor
Patent: 5,717,628 →
Application: 08/606,469 →
Etching High Aspect Contact Holes in Solid State Devices
Patent: 6,008,121 →
Application: 08/618,161 →
Automated Non-Visual Method of Locating Periodically Arranged Sub-Micron Objects
Patent: 5,747,802 →
Application: 08/626,192 →
Controlled Recrystallization of Buried Strap in a Semiconductor Memory Device
Patent: 5,670,805 →
Application: 08/643,983 →
Polycide Etching with Hcl and Chlorine
Patent: 5,874,363 →
Application: 08/645,458 →
Method for Fabricating a Titanium Resistsor
Patent: 5,899,724 →
Application: 08/647,392 →
Uniform Trench Fill Recess by Means of Isotropic Etching
Patent: 5,683,945 →
Application: 08/648,791 →
Three-Dimensional Device Layout Having a Trench Capacitor
Patent: 5,792,685 →
Application: 08/667,541 →
Method of Manufacturing an Insulated Gate Field Effect Transistor
Patent: 5,824,580 →
Application: 08/688,346 →
Insulated Gate Field Effect Transistor
Patent: 5,757,059 →
Application: 08/688,457 →
Integrated Circuit Chip Having Isolation Trenches Composed of a Dielectric Layer with Oxidation Catalyst Material
Patent: 5,721,448 →
Application: 08/688,458 →
Low Pressure and Low Power C12/HC1 Process for Sub-Micron Metal Etching
Patent: 5,976,986 →
Application: 08/689,174 →
Preparation of Poly-O-Hydroxyamides and Poly-O-Mercaptoamides
Patent: 5,760,162 →
Application: 08/703,754 →
Nitride Cap Formation in a Dram Trench Capacitor
Patent: 5,937,292 →
Application: 08/730,839 →
Method for Suppressing Pattern Distortion Associated with Bpsg Reflow and Integrated Circuit Chip Formed Thereby
Patent: 5,973,385 →
Application: 08/736,301 →
Three-Dimensional Device Layout with Sub-Groundrule Features
Patent: 5,893,735 →
Application: 08/742,533 →
Method of Making an Aluminum Contact
Patent: 5,854,140 →
Application: 08/764,382 →
Uniform Distribution of Reactants in a Device Layer
Patent: 5,807,792 →
Application: 08/768,826 →
Memory Cell That Includes a Vertical Transistor and a Trench Capacitor
Patent: 5,937,296 →
Application: 08/770,962 →
Pad Stack with a Poly Si Etch Stop for Teos Mask Removal with Rie
Patent: 5,776,808 →
Application: 08/777,156 →
Application of Thin Crystalline SI3N4 Liners in Shallow Trench Isolation (Sti) Structures
Patent: 5,747,866 →
Application: 08/785,322 →
Shallow Trench Isolation with Oxide-Nitride/Oxynitride Liner
Patent: 5,763,315 →
Application: 08/790,266 →
Control of Gas Content in Process Liquids for Improved Megasonic Cleaning of Semiconductor Wafers and Microelectronics Substrates
Patent: 5,800,626 →
Application: 08/801,685 →
Crack Stops
Patent: 5,789,302 →
Application: 08/823,668 →
Flexible Fuse Placement in Redunant Semiconductor Memory
Patent: 5,859,801 →
Application: 08/825,312 →
Method for Forming a Structure
Patent: 5,926,716 →
Application: 08/829,255 →
Method for Forming Metallization in Semiconductor Devices with a Self- Planarizing Material
Patent: 5,854,126 →
Application: 08/829,257 →
Device with Asymmetrical Channel Dopant Profile
Patent: 6,025,224 →
Application: 08/829,371 →
Etching of Contact Holes
Patent: 6,025,116 →
Application: 08/829,575 →
Method for Forming Deep Depletion Mode Dynamic Random Access Memory (Dram) Cell
Patent: 6,054,345 →
Application: 08/833,557 →
Method of Planarizing the Semiconductor Structure
Patent: 5,963,837 →
Application: 08/846,924 →
Integrated Circuits and Manufacturing Methods
Patent: 6,492,282 →
Application: 08/846,925 →
Integrated Multi-Layer Test Pads
Patent: 5,917,197 →
Application: 08/861,465 →
Single- Electron Memory Cell Configuration
Patent: 5,844,834 →
Application: 08/867,114 →
Semiconductor Structure for an Mos Transistor and Method for Fabricating the Semiconductor Structure
Patent: 5,817,570 →
Application: 08/870,121 →
Buried Strap Formation in a Dram Trench Capacitor
Patent: 5,844,266 →
Application: 08/879,871 →
Leadframe for Semiconductor Chips and Semiconductor Module Having the Lead Frame
Patent: 6,144,088 →
Application: 08/898,734 →
Fuse Refresh Circuit
Patent: 5,905,687 →
Application: 08/904,500 →
Fuse Window with Controlled Fuse Oxide Thickness
Patent: 5,872,390 →
Application: 08/911,542 →
Current-Mode Sense Amplifier
Patent: 5,929,658 →
Application: 08/921,818 →
Circuit and Method to Externally Adjust Internal Circuit Timing
Patent: 5,903,512 →
Application: 08/923,593 →
Threshold Logic Circuit with Low Space Requirement
Patent: 5,986,464 →
Application: 08/959,257 →
Method for Testing a Memory Chip, Divided into Cell Arrays, During Ongoing Operation of a Computer While Maintaining Real-Time Conditions
Patent: 5,937,367 →
Application: 08/963,590 →
Slaves Station with Two Output Circuits Commonly and Directly Connected to a Line for Serially Transmitting Data to a Master Station in Two Operational Modes
Patent: 6,209,022 →
Application: 08/987,886 →
Synthesis of Polybenzoxasole and Polybenzothiazole Precursors
Patent: 5,883,221 →
Application: 08/988,023 →
Shallow Trench Isolation with Oxide-Nitride/Oxynitride Liner
Patent: 6,046,487 →
Application: 08/989,303 →
Method for Producing a Noble Metal-Containing Structure on a Substrate, and Semiconductor Component Having Such a Noble Metal- Containing Structure
Patent: 6,037,256 →
Application: 09/015,452 →
Method for Manufacturing a Capacitor for a Semiconductor Arrangement
Patent: 6,022,786 →
Application: 09/032,484 →
Production Process for a Capacitor Electrode Formed of a Platinum Metal
Patent: 6,136,659 →
Application: 09/047,850 →
Input Amplifier for Input Signals with Steep Edges
Patent: 6,008,695 →
Application: 09/054,926 →
Input Amplifier with Unilateral Current Shutoff for Input Signals with Steep Edges
Patent: 6,020,766 →
Application: 09/054,927 →
Method for Creating a Conductive Connection Between at Least Two Zones of a First Conductivity Type
Patent: 5,998,254 →
Application: 09/055,800 →
Circuit Configuration for Generating an Internal Supply Voltage
Patent: 6,194,953 →
Application: 09/063,314 →
Chemically Amplified Resist
Patent: 6,251,558 →
Application: 09/065,010 →
An Integrated Circuit Arrangement Having at Least One Mos Transistor Manufactured by Use of a Planar Transistor Layou
Patent: 6,066,876 →
Application: 09/065,173 →
Method of Producing a Platinum-Metal Pattern or Structure by a Lift-Off Process
Patent: 6,051,485 →
Application: 09/066,245 →
Method for Producing a Cmos Circuit
Patent: 5,913,115 →
Application: 09/067,766 →
Dram Cell Configuration and Method for Its Production
Patent: 6,255,684 →
Application: 09/071,798 →
Integrated Circuit Having at Least Two Vertical Mos Transistors and Method for Manufacturing Same
Patent: 6,376,313 →
Application: 09/079,020 →
Dram Cell Arrangement Having Dynamic Self-Amplifying Memory Cells, and Method for Manufacturing Same
Patent: 6,049,105 →
Application: 09/089,539 →
Dram Cell Configuration and Method for Its Fabrication
Patent: 6,087,692 →
Application: 09/093,572 →
Circuit Configuration for Generating Digital Signals
Patent: 6,064,228 →
Application: 09/095,261 →
Dram Cell Arrangement and Method for Its Fabrication
Patent: 6,075,265 →
Application: 09/105,235 →
Method of Producing a Barrier Layer in a Semiconductor Body
Patent: 6,100,187 →
Application: 09/106,237 →
Redundancy Circuit for Semiconductor Memories
Patent: 6,188,617 →
Application: 09/115,618 →
Configuration for the Automatic Inscription or Reinscription of Wafers
Patent: 6,147,321 →
Application: 09/128,387 →
Structuring Process
Patent: 6,296,777 →
Application: 09/128,388 →
Structuring Method
Patent: 6,454,956 →
Application: 09/128,389 →
Databus
Patent: 6,060,908 →
Application: 09/128,806 →
Method and Circuit Configuration for Processing Digital Signals
Patent: 6,445,753 →
Application: 09/128,807 →
Circuit Apparatus for Evaluating the Data Content of Memory Cells
Patent: 6,097,650 →
Application: 09/133,704 →
Semiconductor Component and Method for Testing and Operating a Semiconductor Component
Patent: 6,313,655 →
Application: 09/133,893 →
Circuit Arrangement with at Least Four Transistors, and Method for the Manufacture Thereof
Patent: 6,060,911 →
Application: 09/138,160 →
Dram Cell Arrangement and Method for the Manufacture Thereof
Patent: 6,172,391 →
Application: 09/140,972 →
Fuse Configuration for a Semiconductor Storage Device
Patent: 6,180,992 →
Application: 09/143,122 →
Structuring Method
Patent: 6,315,913 →
Application: 09/146,636 →
Method for Producing Structures Having a High Aspect Ratio and Structure Having a High Aspect Ratio
Patent: 6,210,595 →
Application: 09/149,829 →
Level Converting Circuit
Patent: 5,994,944 →
Application: 09/150,789 →
O-Amino (Thio) Phenolcarboxylic Acids and Their Preparation
Patent: 5,998,662 →
Application: 09/160,875 →
Rs Flip-Flop with Enable Inputs
Patent: 5,994,936 →
Application: 09/160,880 →
Pointer Circuit with Low Surface Requirement Hogh Speed and Low Power Loss
Patent: 6,097,661 →
Application: 09/161,004 →
Bis-O-Amino(Thio)Phenols, and Their Preparation
Patent: 6,150,558 →
Application: 09/161,144 →
O-Amino (Thio) Phenolcarboxylic Acids, and Their Preparation
Patent: 6,310,238 →
Application: 09/161,147 →
Polybenzoxazole and Polybenzothiazole Precursors
Patent: 6,153,350 →
Application: 09/161,148 →
O-Nitro(Thio)Phenol Derivatives, and Their Preparation
Patent: 6,320,081 →
Application: 09/161,149 →
Capacitor Having a Barrier Layer Made of a Transition Metal Phosphide, Arsenide or Sulfide
Patent: 7,122,856 →
Application: 09/161,196 →
Polybenzoxazole and Polybenzothiazole Precursors
Patent: 6,120,970 →
Application: 09/161,202 →
Bis-O-Amino (Thio) Phenols, and Their Preparation
Patent: 6,156,902 →
Application: 09/161,549 →
Associative Memory and Method for the Operation Thereof
Patent: 6,160,729 →
Application: 09/162,608 →
Method for the Linear Configuration of Metallic Fuse Sections on Wafers
Patent: 6,698,086 →
Application: 09/163,874 →
Process for Producing a Ceramic Layer
Patent: 6,156,673 →
Application: 09/164,115 →
Process for Producing a Ceramic Layer Containing Bi
Patent: 6,126,998 →
Application: 09/164,119 →
Communications System with a Master Station and at Least One Slave Station
Patent: 6,189,059 →
Application: 09/170,184 →
Integrated Circuit Configuration Having at Least One Capacitor and Method for Producing the Same
Patent: 6,441,424 →
Application: 09/176,558 →
Read Amplifier for Semiconductor Memory Cells with Means to Compensate Threshold Voltage Differences in Read Amplifier Transistors
Patent: 6,028,803 →
Application: 09/180,665 →
Dram Cell Arrangement and Method for the Production Thereof
Patent: 5,977,589 →
Application: 09/191,482 →
Integrated Semiconductor Circuit Having at Least Two Supply Networks
Patent: 6,445,091 →
Application: 09/197,369 →
Microstructure and Methods for Fabricating Such Structure
Patent: 6,015,988 →
Application: 09/197,391 →
Sram Cell Configuration and Method for Its Fabrication
Patent: 6,038,164 →
Application: 09/200,071 →
Chemically Amplified Resist
Patent: 6,171,755 →
Application: 09/201,728 →
Memory Cell Using Amorphous Material to Stabilize the Boundary Face Between Polychrystalline Semiconductor Material of a Capacitor and Moncrystalline Semiconductor Material of a Transistor
Patent: 6,583,464 →
Application: 09/201,733 →
Redundancy Concept for Memory Circuits Having Rom Memory Cells
Patent: 5,986,952 →
Application: 09/204,927 →
Memory Cell Configuration, Method for Fabricating It and Methods for Operating It
Patent: 6,229,169 →
Application: 09/213,724 →
Lead Frame for the Installation of an Integrated Circuit in an Injection-Molded Package
Patent: 6,614,100 →
Application: 09/220,745 →
Integrated Semiconductor Circuit Housing
Patent: 6,057,595 →
Application: 09/221,774 →
Process for Manufacturing a Capacitor in a Semiconductor Arrangement Including Forming a Statistical Hsg Mask of Silicon and Germanium Nuclei
Patent: 6,140,177 →
Application: 09/242,153 →
Wafer Frame
Patent: 6,218,727 →
Application: 09/246,745 →
Device with Asymmetrical Channel Dopant Profile
Patent: 6,355,954 →
Application: 09/251,616 →
Method for Producing a Dram Cellular Arrangement
Patent: 6,037,209 →
Application: 09/254,696 →
Integrated Multi-Layer Test Pads and Methods Therefor
Patent: 5,981,302 →
Application: 09/256,048 →
Memory Cell That Includes a Vertical Transistor and a Trench Capacitor
Patent: 6,200,851 →
Application: 09/272,217 →
Memory Cell That Includes a Vertical Transistor and a Trench Capacitor
Patent: 6,150,210 →
Application: 09/272,218 →
Integrated Circuit with a Housing Accommodating the Integrated Circuit
Patent: 6,573,593 →
Application: 09/272,668 →
Method for Producing Barrier-Free Semiconductor Memory Configurations
Patent: 6,168,988 →
Application: 09/281,691 →
Integrated Semiconductor Memory Configuration with a Buried Plate Electrode and Method for Its Fabrication
Patent: 6,627,934 →
Application: 09/281,696 →
Method for the Production of an Integrated Semiconductor Memory Configuration
Patent: 6,197,633 →
Application: 09/281,822 →
Memory Configuration with Self-Aligning Non-Integrated Capacitor Configuration
Patent: 6,097,050 →
Application: 09/282,041 →
Process for Producing High-Epsilon Dielectric Layer or Ferroelectric Layer
Patent: 6,346,424 →
Application: 09/282,094 →
Process for Producing Barrier-Free Semiconductor Memory Configurations
Patent: 6,297,526 →
Application: 09/282,097 →
Semiconductor Configuration with a Protected Barrier for a Stacked Cell
Patent: 6,043,529 →
Application: 09/282,099 →
Method for Manufacturing an Integrated Circuit Arrangement Having at Least One Mos Transistor
Patent: 6,274,431 →
Application: 09/301,108 →
Method of Minimizing the Access Time in Semiconductor Memories
Patent: 6,285,621 →
Application: 09/373,476 →
O-Amino(Thio) Phenolcarboxylic Acids, and Their Preparation
Patent: 6,096,921 →
Application: 09/388,274 →
Data Memory
Patent: 6,115,286 →
Application: 09/392,767 →
Method of Testing an Integrated Circuit Having a Memory and a Test Circuit
Patent: 6,158,029 →
Application: 09/395,320 →
Input Circuit for an Integrated Circuit
Patent: 6,137,314 →
Application: 09/450,403 →
Configuration of Memory Cells and Method of Checking the Operation of Memory Cells
Patent: 6,279,129 →
Application: 09/465,726 →
Method of producing a vertical mos transistor
Patent: 6,337,247 →
Application: 09/487,411 →
Wafer marking
Patent: 6,261,382 →
Application: 09/495,795 →
Integrated electrical circuit with passivation layer
Patent: 6,395,454 →
Application: 09/498,532 →
Digital circuit having a filter unit for suppressing glitches
Patent: 6,389,086 →
Application: 09/521,396 →
Memory Cell Configuration, Magnetic Ram, and Associative Memory
Patent: 6,490,190 →
Application: 09/528,159 →
Memory Cell Configuration and Fabrication Method
Patent: 6,417,043 →
Application: 09/528,268 →
Dynamic memory having two modes of operation
Patent: 6,191,985 →
Application: 09/528,424 →
Digital memory and method of operation for a digital memory
Patent: 6,208,562 →
Application: 09/536,029 →
Product Including a Silicon-Containing Functional Layer and an Insulating Layer Made of Silicon Dioxide, and Method Fabricating the Product
Patent: 6,410,407 →
Application: 09/539,235 →
Method of Producing an Open Form
Patent: 6,468,348 →
Application: 09/539,237 →
Memory cell configuration
Patent: 6,351,408 →
Application: 09/544,761 →
Method for testing bus connections of writable and readable integrated electronic circuits, in particular memory components
Patent: 6,345,372 →
Application: 09/547,683 →
Integrated Circuit Having a Diffusion Blocker Configured as a Blocker Layer and Connection Pieces Composed of Aluminum Covering Contact Holes and Methods for Fabricating the Same
Patent: 7,064,439 →
Application: 09/595,860 →
Dram Including an Address Space Divided into Individual Blocks Having Memory Cells Activated by Row Address Signals
Patent: 37,930 →
Application: 09/677,368 →
Method of programming a semiconductor memory
Patent: 6,274,410 →
Application: 09/729,068 →
Publication: US 2001/0000758
Method for the Production of a Dram Cell Configuration
Patent: 6,420,228 →
Application: 09/851,051 →
Process for Producing an Integrated Semiconductor Memory Configuration
Patent: 6,605,505 →
Application: 09/883,011 →
Publication: US 2001/0039106
Method of Structuring Layers with a Polysilicon Layer and an Overlying Metal or Metal Silicide Layer Using a Three Step Etching Process with Fluorine, Chlorine, Bromine Containing Gases
Patent: 6,479,373 →
Application: 09/884,188 →
Publication: US 2002/0016044
O-Aminophenolcarboxylic Acid and O-Aminothiophenolcarboxylic Acid
Patent: 6,437,178 →
Application: 09/901,218 →
Publication: US 2001/0056203
Integrated Circuit Having at Least Two Vertical Mos Transistors and Method for Manufacturing Same
Patent: 6,566,202 →
Application: 10/081,902 →
Publication: US 2002/0094628
Cvd Method of Producing in Situ-Doped Polysilicon Layers and Polysilicon Layered Structures
Patent: 6,693,022 →
Application: 10/226,764 →
Publication: US 2003/0017684
Related Assignments (6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest Jul 28, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036201/0432 →
Assignment of Assignor's Interest Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Assignment of Assignor's Interest Dec 7, 2015
From: INFINEON TECHNOLOGIES AG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037221/0885 →
Release of Security Interest May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →