IP Library Granted Patent US 7,122,856
Granted Patent B1
US 7,122,856 · App. 09/161,196 · Granted Oct 17, 2006

Capacitor having a barrier layer made of a transition metal phosphide, arsenide or sulfide

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Quick Facts
Patent No.
US 7,122,856
App. No.
09/161,196
Granted
Oct 17, 2006
Kind
B1
Abstract

The capacitor has a capacitor dielectric formed, in particular, as a high-□-dielectrical or ferroelectrical layer. A barrier layer is formed of a compound of a transition element with phosphorus, sulfur or arsenic. The barrier layer is underneath the capacitor dielectric. The barrier layer is oxygen-impermeable and thus prevents the oxidation of deep structures during high-temperature processes, in particular during the production of the capacitor dielectric.

Claims (17)

1. A capacitor in an integrated semiconductor circuit, comprising:

a semiconductor substrate having a doped region formed therein;

a first electrode connected to said doped region;

a second electrode;

a capacitor dielectric insulating said first electrode from said second electrode; and

a barrier layer disposed below said capacitor dielectric, said barrier layer consisting essentially of a compound formed from a transition element and a material selected from the group consisting of phosphorus, sulfur, and arsenic.

2. The capacitor according to claim 1 , wherein said first electrode is directly connected to said doped region.

3. The capacitor according to claim 1 , which further comprises a connection structure connecting said first electrode to said doped region.

4. The capacitor according to claim 1 , wherein said barrier layer is disposed directly underneath said capacitor dielectric and covers an entire interface between said first electrode and said capacitor dielectric.

5. The capacitor according to claim 3 , wherein said barrier layer is disposed underneath said first electrode and covers an entire interface between said first electrode and said connection structure.

6. The capacitor according to claim 1 , wherein said barrier layer is disposed underneath said first electrode and covers an entire interface between said first electrode and said doped region.

7. The capacitor according to claim 1 , wherein said capacitor dielectric consists of a material selected from the group consisting of dielectric material and ferroelectric material, and has a value of □>100.

8. The capacitor according to claim 1 , wherein said capacitor dielectric consists of a material selected from the group consisting of BST, SBT, PZT, and PLT.

9. The capacitor according to claim 1 , wherein said first electrode consists of a material selected from the group consisting of Pt-containing material, Ru-containing material, Rh-containing material, and Ir-containing material.

10. The capacitor according to claim 3 , wherein said connection structure is made of a material selected from the group consisting of polysilicon and tungsten.

11. The capacitor according to claim 1 , wherein said barrier layer is essentially a layer selected from the group consisting of a tungsten phosphide layer, a tantalum phosphide layer, and a hafnium phosphide layer.

12. A semiconductor configuration, comprising a capacitor according to claim 1 , and an associated selection transistor which encompasses said doped region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023963/0502 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2010
From: SIEMENS AKTIENGESELLSCHAFT
To: INFINEON TECHNOLOGIES AG
Reel/Frame 024120/0505 →