IP Library › Assignment 036201/0432
Patent Assignment
Reel/Frame 036201/0432

Assignment of Assignor's Interest

Recorded: 2015-07-28 Pages: 11
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties (140)
Unit Cell Layout and Transfer Gate Design for High Density Drams Having a Trench Capacitor with Signal Electrode Composed of Three Diffently Doped Polysilicon Layers
Patent: 5,936,271 →
Application: 08/340,500 →
Photoresists Which Are Suitable for Producing Sub-Micron Size Structures
Patent: 6,110,637 →
Application: 08/386,136 →
Copolymers
Patent: 5,616,667 →
Application: 08/434,955 →
Multilayer Printed Circuit Boards and Multichip-Module Substrates with Layers of Amorphous Hydrogenated Carbon
Patent: 5,601,902 →
Application: 08/443,298 →
Connection and Build-Up Technique for Multichip Modules
Patent: 5,556,812 →
Application: 08/495,246 →
Module Board Including Conductor Tracks Having Disconnectable Connecting Elements
Patent: 5,572,457 →
Application: 08/498,165 →
Method for Hierarchic Logic Verification of Vlsi Circuits
Patent: 5,671,399 →
Application: 08/498,687 →
Off-State Gate-Oxide Field Reduction in Cmos
Patent: 5,602,410 →
Application: 08/519,669 →
Etch Chamber Having Three Independently Controlled Electrodes
Patent: 5,597,438 →
Application: 08/527,909 →
Formation of Self-Aligned Overlapping Bitline Contacts with Sacrificial Polysilicon Fill-in Stud
Patent: 5,723,381 →
Application: 08/534,776 →
Process for Depositing a Surface-Wide Layer Through a Mask and Optionally Closing Said Mask
Patent: 5,786,235 →
Application: 08/537,915 →
Contact Structure for Vertical Chip Connections
Patent: 5,846,879 →
Application: 08/545,647 →
Process for Producing Semiconductor Components Between Which Contact Is Made Vertically
Patent: 5,767,001 →
Application: 08/545,650 →
Integrated Polysilicon Diode Contact for Gain Memory Cells
Patent: 5,710,448 →
Application: 08/549,885 →
Transistor Isolation Process
Patent: 5,854,112 →
Application: 08/563,882 →
Flexible Ecc/Parity Bit Architecture
Patent: 5,966,389 →
Application: 08/603,409 →
Test Circuit and Testing Method for Function Testing of Electronic Circuits
Patent: 6,107,815 →
Application: 08/605,901 →
Board Having a Plurality of Integrated Circuits
Patent: 5,818,779 →
Application: 08/610,046 →
Semiconductor Memory with Cells Combined into Individually Addressable Units, and Method for Operating Such Memories
Patent: 5,671,184 →
Application: 08/610,047 →
Semiconductor Component with Protective Structure for Protecting Against Electrostatic Discharge
Patent: 5,646,434 →
Application: 08/610,523 →
An Integrated Circuit Board with Built-in Terminal Connection Testing Circuitry
Patent: 5,815,001 →
Application: 08/617,125 →
Methods for Producing Polybenzoxazol Precursors and Corresponding Resist Solutions
Patent: 5,688,631 →
Application: 08/618,488 →
Low Power Sense Amplifier for Gain Memory Cells
Patent: 5,610,540 →
Application: 08/625,840 →
Serially Accessible Memory Means with High Error Correctability
Patent: 5,751,742 →
Application: 08/626,512 →
Integrated Semiconductor Circuit
Patent: 5,821,804 →
Application: 08/629,184 →
Prevention of Abnormal Wsix Oxidation by in-Situ Amorphous Silicon Deposition
Patent: 5,804,499 →
Application: 08/642,294 →
Dram Cell Arrangement and Method for Its Manufacture
Patent: 5,736,761 →
Application: 08/645,503 →
Apparatus and Method for Cleaning Photomasks
Patent: 5,634,230 →
Application: 08/647,154 →
Integrated Circuit and Method for Producing the Same
Patent: 5,726,601 →
Application: 08/647,464 →
Uniform Trench Fill Recess by Means of Isotropic Etching
Patent: 5,683,945 →
Application: 08/648,791 →
Semiconductor Array with Self-Adjusted Contacts
Patent: 5,864,155 →
Application: 08/651,305 →
Memory Apparatus with Dynamic Memory Cells Having Different Capacitor Values
Patent: 5,706,225 →
Application: 08/652,915 →
Method for the Production of Poly-0-Hydroxyamides
Patent: 5,750,638 →
Application: 08/666,177 →
Method for the Production of Poly-O-Hydroxyamides
Patent: 5,777,066 →
Application: 08/666,182 →
Fuse Bank
Patent: 5,661,331 →
Application: 08/671,796 →
Bootstrap Circuit and Integrated Memory Circuit Having the Bootstrap Circuit
Patent: 5,783,962 →
Application: 08/679,372 →
Unit Cell Layout and Transfer Gate Design for High Density Drams
Patent: 6,004,844 →
Application: 08/680,765 →
Integrated Switching Circuit with Cmos Circuit and Method for Producing Isolated Active Regions of a Cmos Circuit
Patent: 5,847,433 →
Application: 08/681,296 →
Memory Cell Arrangement of Memory Cells Arranged in the Form of a Matrix
Patent: 5,825,701 →
Application: 08/682,022 →
Capacitor in a Semiconductor Configuration and Process for Its Production
Patent: 5,989,972 →
Application: 08/685,847 →
Integrated Circuit
Patent: 5,789,932 →
Application: 08/689,208 →
Gapfilll and Planarization Process for Shallow Trench Isolation
Patent: 5,851,899 →
Application: 08/694,072 →
Memory Device and Production Method
Patent: 5,774,414 →
Application: 08/694,531 →
Integrated Semiconductor Memory Device
Patent: 5,675,543 →
Application: 08/694,533 →
Integrated Semiconductor Memory
Patent: 5,666,316 →
Application: 08/694,534 →
Preparation of Poly-O-Hydroxyamides and Poly-O-Mercaptoamides
Patent: 5,760,162 →
Application: 08/703,754 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent: 5,973,202 →
Application: 08/704,064 →
Novel Dicarboxylic Acid Derivatives
Patent: 5,750,711 →
Application: 08/704,213 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent: 5,807,969 →
Application: 08/705,099 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent: 5,922,825 →
Application: 08/705,446 →
Preparation of Poly-O-Hydroxyamides and Poly-O-Mercaptoamides
Patent: 5,696,218 →
Application: 08/705,469 →
Preparation of Poly-O-Hydroxymides and Poly O-Mercaptoamides
Patent: 5,783,654 →
Application: 08/705,575 →
Preparation of Poly-O-Hydroxyamides and Poly O-Mercaptoamides
Patent: 5,726,279 →
Application: 08/705,576 →
A Semiconductor Configuration for an Insulating Transistor
Patent: 5,962,901 →
Application: 08/715,932 →
Low Loss Integrated Circuit with Reduced Clock Swing
Patent: 5,854,567 →
Application: 08/716,440 →
Mixed Polymers
Patent: 5,703,186 →
Application: 08/717,652 →
Dram Cell Array with Dynamic Gain Memory Cells
Patent: 5,854,500 →
Application: 08/721,546 →
Integrated Circuit Interconnection Employing Tungsten/Aluminum Layers
Patent: 5,840,625 →
Application: 08/726,443 →
Microelectronic Component and Process for Its Production
Patent: 5,828,076 →
Application: 08/727,440 →
A Semiconductor Memory Device Having a Transistor, a Bit Line, a Word- Line and a Stacked Capacitor
Patent: 5,714,779 →
Application: 08/730,644 →
Method of Producing and Arrangement Containing Self-Amplifying Dynamic Mos Transistor Memory Cells
Patent: 5,710,072 →
Application: 08/737,236 →
Dry-Developable Positive Resist
Patent: 5,733,706 →
Application: 08/737,989 →
Formation of Silicided Junctions in Deep Submicron Mosfets by Defect Enhanced COS12 Formation
Patent: 5,780,929 →
Application: 08/744,132 →
Process for Manufacturing Capacitors in a Solid State Configuration
Patent: 5,817,553 →
Application: 08/766,977 →
Uniform Distribution of Reactants in a Device Layer
Patent: 5,807,792 →
Application: 08/768,826 →
Method for Producing a Contact Hole to a Doped Region
Patent: 5,731,218 →
Application: 08/769,311 →
Memory Cell That Includes a Vertical Transistor and a Trench Capacitor
Patent: 5,937,296 →
Application: 08/770,962 →
Apparatus and Method for Detecting and Assessing a Spatially Discrete Dot Pattern
Patent: 5,950,181 →
Application: 08/779,365 →
Double Density Fuse Bank for the Laser Break-Link Programming of an Integrated Circuit
Patent: 5,773,869 →
Application: 08/780,242 →
Method of Amufacturing a Fuse Structure
Patent: 5,827,759 →
Application: 08/781,571 →
Photolithographic Pattern Generation
Patent: 5,851,733 →
Application: 08/793,310 →
Photolithographic Pattern Generation
Patent: 5,863,705 →
Application: 08/793,546 →
Fuse Structure for an Integrated Circuit Element
Patent: 5,789,794 →
Application: 08/811,327 →
Read-Only-Memory Cell Arrangement Using Vertical Mos Transistors and Gate Dielectrics of Different Thicknesses and Method for Its Production
Patent: 5,973,373 →
Application: 08/817,630 →
Portable Data Carrier Configuration to Be Operated on a Data Bus and Data Processing System Having at Least One Portable Data Carrier Configuration
Patent: 5,884,319 →
Application: 08/828,538 →
Data Carrier Card, Assembly of at Least Two Data Carrier Cards and Method of Accessing at Least One of the Data Carrier Cards
Patent: 5,925,928 →
Application: 08/828,697 →
Method for Forming Deep Depletion Mode Dynamic Random Access Memory (Dram) Cell
Patent: 6,054,345 →
Application: 08/833,557 →
Single- Electron Memory Cell Configuration
Patent: 5,844,834 →
Application: 08/867,114 →
Semiconductor Structure for an Mos Transistor and Method for Fabricating the Semiconductor Structure
Patent: 5,817,570 →
Application: 08/870,121 →
Multi-Value Read-Only Memory Cell Having an Improved Signal-to-Noise Ratio
Patent: 5,825,686 →
Application: 08/875,955 →
Photolithographic Structure Generation Process
Patent: 6,042,993 →
Application: 08/875,957 →
Double Density Fuse Bank for the Laser Break-Link Programming of an Integrated Circuit
Patent: 5,933,714 →
Application: 08/879,875 →
Semiconductor Memory Device with Trench Capacitor and Method for the Production Thereof
Patent: 5,843,819 →
Application: 08/898,514 →
Leadframe for Semiconductor Chips and Semiconductor Module Having the Lead Frame
Patent: 6,144,088 →
Application: 08/898,734 →
Fuse Refresh Circuit
Patent: 5,905,687 →
Application: 08/904,500 →
Current-Mode Sense Amplifier
Patent: 5,929,658 →
Application: 08/921,818 →
Gtl Output Amplifier for Coupling an Input Signal at the Input to a Transmission Line at the Output
Patent: 6,075,383 →
Application: 08/930,535 →
Threshold Logic Circuit with Low Space Requirement
Patent: 5,986,464 →
Application: 08/959,257 →
Method for Testing a Memory Chip, Divided into Cell Arrays, During Ongoing Operation of a Computer While Maintaining Real-Time Conditions
Patent: 5,937,367 →
Application: 08/963,590 →
Slaves Station with Two Output Circuits Commonly and Directly Connected to a Line for Serially Transmitting Data to a Master Station in Two Operational Modes
Patent: 6,209,022 →
Application: 08/987,886 →
Synthesis of Polybenzoxasole and Polybenzothiazole Precursors
Patent: 5,883,221 →
Application: 08/988,023 →
Device in a Semicondutor Manufacturing Installation in Particular for Integrated Circuits
Patent: 6,075,358 →
Application: 09/005,067 →
Method for Suppressing Pattern Distortion Associated with Bpsg Reflow
Patent: 5,994,215 →
Application: 09/009,198 →
Integrated Circuit with Esd Protection
Patent: 5,929,491 →
Application: 09/009,602 →
Method for Producing a Noble Metal-Containing Structure on a Substrate, and Semiconductor Component Having Such a Noble Metal- Containing Structure
Patent: 6,037,256 →
Application: 09/015,452 →
Manufacturing Process for a Raised Capacitor Electrode
Patent: 6,004,856 →
Application: 09/022,686 →
Integrated Circuit Interconnection Employing Tungsten / Aluminum Layers
Patent: 6,016,008 →
Application: 09/024,998 →
Method for Manufacturing a Capacitor for a Semiconductor Arrangement
Patent: 6,022,786 →
Application: 09/032,484 →
Device for the Jump-Like Addressing of Specific Lines of a Serially Operating Digital Memory
Patent: 6,138,227 →
Application: 09/043,046 →
Production Process for a Capacitor Electrode Formed of a Platinum Metal
Patent: 6,136,659 →
Application: 09/047,850 →
Read Only Memory
Patent: 5,943,255 →
Application: 09/049,558 →
Double Density Fuse Bank for the Laser Break-Link Programming of an Integrated Circuit
Patent: 5,986,321 →
Application: 09/053,922 →
Input Amplifier for Input Signals with Steep Edges
Patent: 6,008,695 →
Application: 09/054,926 →
Input Amplifier with Unilateral Current Shutoff for Input Signals with Steep Edges
Patent: 6,020,766 →
Application: 09/054,927 →
Method for Creating a Conductive Connection Between at Least Two Zones of a First Conductivity Type
Patent: 5,998,254 →
Application: 09/055,800 →
Circuit Configuration for Generating an Internal Supply Voltage
Patent: 6,194,953 →
Application: 09/063,314 →
An Integrated Circuit Arrangement Having at Least One Mos Transistor Manufactured by Use of a Planar Transistor Layou
Patent: 6,066,876 →
Application: 09/065,173 →
Method of Producing a Platinum-Metal Pattern or Structure by a Lift-Off Process
Patent: 6,051,485 →
Application: 09/066,245 →
Method for Producing a Memory Device
Patent: 6,100,109 →
Application: 09/081,910 →
Method for Operating a Sram Mos Transistor Memory Cell
Patent: 5,973,965 →
Application: 09/091,713 →
Read-Only Memory Cell Device and Method for Its Production
Patent: 6,211,019 →
Application: 09/130,051 →
Communications System with a Master Station and at Least One Slave Station
Patent: 6,189,059 →
Application: 09/170,184 →
Integrated Buffer Circuit
Patent: 6,069,491 →
Application: 09/174,745 →
Read Amplifier for Semiconductor Memory Cells with Means to Compensate Threshold Voltage Differences in Read Amplifier Transistors
Patent: 6,028,803 →
Application: 09/180,665 →
Redundancy Concept for Memory Circuits Having Rom Memory Cells
Patent: 5,986,952 →
Application: 09/204,927 →
Method for Reading and Refreshing a Dynamic Semiconductor Memory
Patent: 5,978,296 →
Application: 09/205,624 →
Lead Frame for the Installation of an Integrated Circuit in an Injection-Molded Package
Patent: 6,614,100 →
Application: 09/220,745 →
Integrated Semiconductor Circuit Housing
Patent: 6,057,595 →
Application: 09/221,774 →
Process for Manufacturing a Capacitor in a Semiconductor Arrangement Including Forming a Statistical Hsg Mask of Silicon and Germanium Nuclei
Patent: 6,140,177 →
Application: 09/242,153 →
Wafer Frame
Patent: 6,218,727 →
Application: 09/246,745 →
Method for Producing a Dram Cellular Arrangement
Patent: 6,037,209 →
Application: 09/254,696 →
Steep Edge Time-Delay Relay
Patent: 6,181,183 →
Application: 09/269,047 →
Memory Cell That Includes a Vertical Transistor and a Trench Capacitor
Patent: 6,200,851 →
Application: 09/272,217 →
Memory Cell That Includes a Vertical Transistor and a Trench Capacitor
Patent: 6,150,210 →
Application: 09/272,218 →
Integrated Circuit with a Housing Accommodating the Integrated Circuit
Patent: 6,573,593 →
Application: 09/272,668 →
Method for Producing Barrier-Free Semiconductor Memory Configurations
Patent: 6,168,988 →
Application: 09/281,691 →
Method for the Production of an Integrated Semiconductor Memory Configuration
Patent: 6,197,633 →
Application: 09/281,822 →
Process for Producing High-Epsilon Dielectric Layer or Ferroelectric Layer
Patent: 6,346,424 →
Application: 09/282,094 →
Process for Producing Barrier-Free Semiconductor Memory Configurations
Patent: 6,297,526 →
Application: 09/282,097 →
Isolation Collar Nitride Liner for Dram Process Improvement
Patent: 6,207,494 →
Application: 09/282,122 →
Method for Manufacturing an Integrated Circuit Arrangement Having at Least One Mos Transistor
Patent: 6,274,431 →
Application: 09/301,108 →
Mosfets with Improved Short Channel Effects and Method of Making the Same
Patent: 6,380,015 →
Application: 09/306,617 →
Method of Minimizing the Access Time in Semiconductor Memories
Patent: 6,285,621 →
Application: 09/373,476 →
Data Memory
Patent: 6,115,286 →
Application: 09/392,767 →
Method of Testing an Integrated Circuit Having a Memory and a Test Circuit
Patent: 6,158,029 →
Application: 09/395,320 →
Dram Including an Address Space Divided into Individual Blocks Having Memory Cells Activated by Row Address Signals
Patent: 37,930 →
Application: 09/677,368 →
Process for Producing an Integrated Semiconductor Memory Configuration
Patent: 6,605,505 →
Application: 09/883,011 →
Publication: US 2001/0039106
Method of Structuring Layers with a Polysilicon Layer and an Overlying Metal or Metal Silicide Layer Using a Three Step Etching Process with Fluorine, Chlorine, Bromine Containing Gases
Patent: 6,479,373 →
Application: 09/884,188 →
Publication: US 2002/0016044
Method for checking a semiconductor memory device
Patent: 6,366,511 →
Application: 09/910,745 →
Publication: US 2001/0040832
Cvd Method of Producing in Situ-Doped Polysilicon Layers and Polysilicon Layered Structures
Patent: 6,693,022 →
Application: 10/226,764 →
Publication: US 2003/0017684
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
Assignment of Assignor's Interest Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest Feb 22, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023963/0502 →
Assignment of Assignor's Interest May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →