Process for producing a doped semiconductor substrate
View Patent ↗A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.
1. A process for producing a doping for a MOS transistor, which comprises the following steps:
providing a semiconductor substrate;
producing a doping at a surface of the semiconductor substrate;
after producing the doping, applying a layer selected from the group consisting of a polycrystalline layer and an amorphous layer to the surface;
performing a rapid thermal annealing process; and
subsequently carrying out a heat treatment step for producing an epitaxial layer and a buried doping for a MOS transistor.
2. The process according to claim 1 , which comprises forming the further amorphous layer to have a thickness of between 500-1000 nm.
3. The process according to claim 1 , which comprises carrying out the rapid thermal annealing process out at a temperature of between 1000° and 1100° C.
4. The process according to claim 1 , which comprises carrying out the rapid thermal annealing process for a time period of between 10 and 60 seconds.
5. The process according to claim 1 , which comprises forming the semiconductor substrate from silicon.
6. The process according to claim 1 , which comprises forming the polycrystalline layer and the amorphous layer from silicon.
7. The process according to claim 1 , which comprises producing the doping by an ion implantation process.
8. The process according to claim 7 , which comprises carrying out the ion implantation process using ions selected from the group consisting of B, P, As, In and Sb ions.
9. A process for producing a doping for a MOS transistor, which comprises the following steps:
providing a semiconductor substrate;
producing the doping, depositing a poly/α layer using a low-pressure and low-temperature chemical vapor deposition process to the surface of the semiconductor substrate; and
carrying out a heat treatment step for producing an eptiaxial layer and a buried doping for a MOS transistor.
10. The process according to claim 9 , which comprises carrying out a crystallization of the poly/α layer by performing a low-temperature step.
11. The process according to claim 10 , which comprises carrying out the low-temperature step at a temperature of between 600° C. to 700° C.
12. The process according to claim 10 , which comprises carrying out a wet etching operation out after performing the a low-temperature step.
13. The process according to claim 10 , which comprises performing the crystallization at a same time as a formation of a gate oxide.
14. The process according to claim 10 , which comprises carrying out the low-temperature step at a temperature of 650° C.
15. The process according to claim 9 , which comprises depositing the poly/α layer at a temperature of between 500° C. and 600° C.
16. A process for producing a doping for a MOS transistor, which comprises the following steps:
providing a semiconductor substrate;
producing a doping at a surface of the semiconductor substrate;
after producing the doping, depositing a poly/α layer to a thickness between 20 nm to 40 nm using a low-pressure chemical vapor deposition process to the surface of the semiconductor substrate; and
carrying out a heat treatment step for producing an epitaxial layer and a buried doping for a MOS transistor.
17. A process for producing a MOS transistor with a buried doping, which comprises the following steps:
providing a semiconductor substrate;
producing a doping at a surface of the semiconductor substrate;
after producing the doping, applying a layer selected from the group consisting of a polycrystalline layer and an amorphous layer to the surface;
subjecting the assembly to ion bombardment or to RTA processing with a rapid heat treatment to thereby destroy an oxide layer present between the semiconductor substrate and the polycrystallinge or amorphous layer; and
subjecting the assembly to a heat treatment step for producing a monocrystalline layer and a buried doping from the layers and the semiconductor substrate for forming the MOS transistor.