Multi-layer electrode and method of forming the same
View Patent ↗An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.
1. An interconnect comprising:
an opening formed in a dielectric layer;
a conductive barrier layer deposited in the opening;
a first conductive layer deposited over the conductive barrier layer;
a conductive liner deposited over the first conductive layer, wherein the conductive liner comprises a conductive oxide; and
a second conductive layer deposited over the conductive liner, the first conductive layer and the second conductive layer comprising the same material and wherein the second conductive layer extends below a major surface of the dielectric layer.
2. The interconnect according to claim 1 , wherein the conductive liner comprises iridium oxide.
3. The interconnect according to claim 1 , wherein the conductive liner comprises ruthenium oxide.
4. The interconnect according to claim 1 , wherein the conductive liner is 20-50 Angstroms thick.
5. The interconnect according to claim 1 , wherein the first conductive layer is about 200-500 Angstroms thick.
6. The interconnect according to claim 1 , wherein the conductive barrier layer comprises TaSiN.
7. The interconnect according to claim 1 , wherein the first conductive layer and the second conductive layer comprise Platinum (Pt), Iridium (Ir), Ruthenium (Ru), or Palladium (Pd).
8. The interconnect according to claim 1 , wherein the conductive barrier layer is formed over polysilicon formed in the opening.
9. A capacitor comprising:
a TaSiN layer;
a first Pt layer overlying the TaSiN layer;
a conductive liner overlying the first Pt layer, the conductive liner comprising a material selected from the group consisting of IrO 2 and RuO 2 ;
a second Pt layer overlying the conductive liner;
a dielectric liner overlying the second Pt layer; and
a conductive electrode overlying the dielectric liner.
10. The capacitor of claim 9 , wherein the capacitor comprises a capacitor of a DRAM cell.
11. The capacitor of claim 9 , wherein the conductive liner is 20-50 Angstroms thick and the first Pt layer is about 200-500 Angstroms thick.
12. An interconnect structure comprising:
a dielectric layer having an opening formed therein;
a barrier liner formed along a surface of the opening;
a multi-layer conductive layer formed over the barrier liner, the multi-layer conductive layer comprising a conductive liner formed between a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer comprising a first material, wherein the first material comprises Platinum (Pt), Iridium (Ir), Ruthenium (Ru), or Palladium (Pd).
13. The interconnect according to claim 12 , wherein the conductive liner is 20-50 Angstroms thick.
14. The interconnect according to claim 12 , wherein the first conductive layer is about 200-500 Angstroms thick.
15. The interconnect according to claim 12 , wherein the barrier liner comprises TaSiN.
16. The interconnect according to claim 12 , wherein the conductive liner comprises a conductive oxide.
17. The interconnect according to claim 12 , wherein the conductive liner comprises iridium oxide.
18. The interconnect of claim 12 , wherein the conductive liner comprises ruthenium oxide.
19. An interconnect comprising:
an opening formed in a dielectric layer;
a conductive barrier layer deposited over the opening, wherein the conductive barrier layer is formed over polysilicon formed in the opening;
a first conductive layer deposited over the conductive barrier layer;
a conductive liner deposited over the first conductive layer; and
a second conductive layer deposited over the conductive liner, the first conductive layer and the second conductive layer comprising the same material and wherein the second conductive layer extends below a major surface of the dielectric layer, and wherein the grain structure of the first and second conductive layers are interrupted by the conductive liner.
20. The interconnect according to claim 19 , wherein the conductive liner comprises a conductive oxide.
21. The interconnect according to claim 20 , wherein the conductive liner comprises iridium oxide.
22. The interconnect according to claim 20 , wherein the conductive liner comprises ruthenium oxide.
23. The interconnect according to claim 20 , wherein the conductive liner is 20-50 Angstroms thick.
24. The interconnect according to claim 19 , wherein the first conductive layer is about 200-500 Angstroms thick.
25. The interconnect according to claim 19 , wherein the conductive barrier layer comprises TaSiN.
26. The interconnect according to claim 19 , wherein the first conductive layer and the second conductive layer comprise Platinum (Pt), Iridium (Ir), Ruthenium (Ru), or Palladium (Pd).