Method for fabricating an integrated semiconductor component
View Patent ↗A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.
1. A method for fabricating an integrated semiconductor component comprising the following steps:
providing a semiconductor layer having a front side and a back side;
forming at least one isolation trench in the front side of the semiconductor layer;
applying a first layer of a non-conductive material of silicon oxide onto the front side of the semiconductor layer using a non-conformal deposition method; and
applying a second layer of a non-conductive material of silicon oxide by a conformal deposition method onto the front side and back side of the semiconductor layer.
2. A method according to claim 1 , wherein the isolation trench has a depth of between 5,000 and 10,000 angstroms.
3. A method according to claim 2 , wherein the isolation trench has a depth of between 6,000 and 8,000 angstroms.
4. A method according to claim 2 , wherein the first layer of non-conductive material has a thickness of between 1,000 and 4,000 angstroms.
5. A method according to claim 4 , wherein the first layer of non-conductive material has a thickness of between 2,000 and 3,000 angstroms.
6. A method according to claim 4 , wherein the second layer of non-conductive material has a thickness of between 1,600 and 5,000 angstroms.
7. A method according to claim 6 , wherein the second layer of non-conductive material has a thickness of between 2,000 and 4,000 angstroms.
8. A method according to claim 1 , wherein the non-conformal method for deposition is selected from a group consisting of high-density plasma chemical vapor deposition (HDP-CVD) and a Selox process.
9. A method according to claim 8 , wherein the conformal method for deposition is selected from a group consisting of atmospheric pressure thermal chemical vapor deposition (APCVD), sub-atmospheric pressure thermal chemical vapor deposition (SACVD) and low-pressure chemical vapor deposition (LPCVD).
10. A method according to claim 9 , wherein the Si source used during the application of the non-conductive layer is tetraethyl orthosilicate (TEOS).
11. A method according to claim 1 , which includes, after the application of the second layer, chemically polishing the second layer.
12. A method according to claim 1 , wherein the first layer of non-conductive material has a thickness of between 1,000 and 4,000 angstroms.
13. A method according to claim 12 , wherein the first layer of non-conductive material has a thickness of between 2,000 and 3,000 angstroms.
14. A method according to claim 1 , wherein the second layer of non-conductive material has a thickness of between 1,000 and 5,000 angstroms.
15. A method according to claim 14 , wherein the second layer of non-conductive material has a thickness of between 2,000 and 4,000 angstroms.
16. A method according to claim 1 , wherein the conformal method for deposition of the second layer of non-conductive material is selected from a group consisting of atmospheric pressure thermal chemical vapor deposition (APCVD), sub-atmospheric pressure thermal chemical vapor deposition (SACVD) and low-pressure chemical vapor deposition (LPCVD).
17. A method according to claim 16 , wherein the Si source used during the application of the non-conductive layer is tetraethyl orthosilicate (TEOS).
18. A method according to claim 1 , wherein the second layer of non-side conductive material seals the back side of the semiconductor layer.