Granted Patent
Utility
US 6,593,228
· Confirmation No. 5660
METHOD OF FABRICATING A PATTERNED METAL-CONTAINING LAYER ON A SEMICONDUCTOR WAFER
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-04-12 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-04-12 | SPEC |
Specification | 17 | View | |
| 2002-04-12 | CLM |
Claims | 4 | View | |
| 2002-04-12 | ABST |
Abstract | 1 | View | |
| 2002-04-12 | DRW |
Drawings-only black and white line drawings | 2 | View | |
| 2002-04-12 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Volker Weinrich
Paris, FRANCE
Gerhard Beitel
Kamakura-shi, JAPAN
Andreas Hauser
Schrobenhausen, GERMANY
Peter Bosk
Dresden, GERMANY
Attorneys & Agents of Record
Classification
USPC
438/633
H10P50/286
H10D1/692
H10P50/71
H10P50/267
H10P52/403
Prosecution
- Examiner
- QUACH, TUAN N
- Art Unit
- 2814
- Docket No.
- P2001,0261
- Confirmation No.
- 5660
Foreign Priority
101 18 422.0
·
2001-04-12
·
GERMANY
Publication
- Pub. No.
- US20020160596A1
- Pub. Date
- 2002-10-31
Patent Term Adjustment
-8days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-09-09
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-05-30
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Quick Facts
- Patent No.
- US 6,593,228
- App. No.
- 10/122,936
- Filed
- 2002-04-12
- Granted
- 2003-07-15
- Pub. No.
- US20020160596A1
- Examiner
- QUACH, TUAN N
- Art Unit
- 2814
- PTA
- -8 days
External Links