Integrated circuit having a data processing unit and a buffer memory

1. An integrated circuit, comprising:

a data processing unit;

a buffer memory having registers for storing data for said data processing unit, said buffer memory connected to said data processing unit; and

a setting memory connected to said buffer memory, said setting memory having at least one electrical fuse being at least one of written to and read from through said buffer memory;

said buffer memory having a shift register, said shift register having at least one switch subdividing said shift register into said registers for said data processing unit.

2. The integrated circuit according to claim 1 , including circuit elements, said setting memory activating said circuit elements.

3. The integrated circuit according to claim 2 , including a memory having memory areas, said circuit elements being memory elements used to replace at least one of said memory areas.

4. The integrated circuit according to claim 1 , wherein said data processing unit has an arithmetic logic unit.

5. The integrated circuit according to claim 4 , wherein

a register of said registers processes data; and

another register of said registers processes coded instructions for said arithmetic logic unit.

6. The integrated circuit according to claim 5 , wherein said buffer memory is two buffer memories each containing data to be processed.

7. The integrated circuit according to claim 1 , wherein said buffer memory is a latch.

8. The integrated circuit according to claim 1 , wherein said data processing unit serially writes to and reads from each of said registers.

9. A method for determining setting data for a setting memory from address data, stored in a register, of memory areas of a memory that have been identified as defective depending on instruction data stored in a register, which comprises:

providing an integrated circuit having:

a data processing unit;

a buffer memory having registers, the buffer memory having a shift register, the shift register having at least one switch subdividing the shift register into the registers; and

a setting memory having electrical fuses;

storing data for the data processing unit in the registers of the buffer memory;

connecting the buffer memory to the data processing unit;

connecting the setting memory to the buffer memory, the setting memory being only accessible via the registers of the buffer memory, the buffer memory being used as latches for reading out and writing into the setting memory; and

at least one of writing to and reading from the setting memory through the buffer memory.

10. The method according to claim 9 , which further comprises activating circuit elements with the setting memory.

11. The method according to claim 10 , wherein the circuit elements are memory elements of a memory and which further comprises replacing at least one of the memory areas with the memory elements.

12. The method according to claim 9 , wherein the data processing unit has an arithmetic logic unit.

13. The method according to claim 12 , which further comprises:

processing data with a register, and

processing coded instructions for the arithmetic logic unit with another register.

14. The method according to claim 13 , wherein the buffer memory is two buffer memories each containing data to be processed.

15. The method according to claim 9 , wherein the buffer memory is a latch.

16. The method according to claim 9 , which further comprises serially writing to and reading from each of the registers with the processing unit.