IP Library Granted Patent US 6,484,307
Granted Patent Utility
US 6,484,307 · Confirmation No. 8639

METHOD FOR FABRICATING AND CHECKING STRUCTURES OF ELECTRONIC CIRCUITS IN A SEMICONDUCTOR SUBSTRATE

⬇ PDF
Code Description Pages PDF
2001-03-19 TRNA Transmittal of New Application 1 View
2001-03-19 SPEC Specification 18 View
2001-03-19 CLM Claims 4 View
2001-03-19 ABST Abstract 1 View
2001-03-19 DRW Drawings-only black and white line drawings 3 View
2001-03-19 OATH Oath or Declaration filed 3 View
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Quick Facts
Patent No.
US 6,484,307
App. No.
09/811,867
Filed
2001-03-19
Granted
2002-11-19
Pub. No.
US20020016693A1
Examiner
VU, JIMMY T
Art Unit
2821
PTA
-120 days