Granted Patent
Utility
US 6,484,307
· Confirmation No. 8639
METHOD FOR FABRICATING AND CHECKING STRUCTURES OF ELECTRONIC CIRCUITS IN A SEMICONDUCTOR SUBSTRATE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-03-19 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-03-19 | SPEC |
Specification | 18 | View | |
| 2001-03-19 | CLM |
Claims | 4 | View | |
| 2001-03-19 | ABST |
Abstract | 1 | View | |
| 2001-03-19 | DRW |
Drawings-only black and white line drawings | 3 | View | |
| 2001-03-19 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Jurgen Karl
Munchen, GERMANY
Martin Zibert
Feldkirchen-Westerham, GERMANY
Valentin Rosskopf
Poettmess-Schorn, GERMANY
Attorneys & Agents of Record
Classification
USPC
716/21
H10P74/277
H10P74/00
Prosecution
- Examiner
- VU, JIMMY T
- Art Unit
- 2821
- Docket No.
- GR 00 P 4055
- Confirmation No.
- 8639
Foreign Priority
100 14 914.6
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2000-03-17
·
GERMANY
Publication
- Pub. No.
- US20020016693A1
- Pub. Date
- 2002-02-07
Patent Term Adjustment
-120days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-09-09
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-10-08
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Quick Facts
- Patent No.
- US 6,484,307
- App. No.
- 09/811,867
- Filed
- 2001-03-19
- Granted
- 2002-11-19
- Pub. No.
- US20020016693A1
- Examiner
- VU, JIMMY T
- Art Unit
- 2821
- PTA
- -120 days
External Links