Method and device for generating digital signal patterns

1. A method for testing dynamic digital circuits by outputting digital electrical signal patterns, which comprises:

providing an addressable memory and a control logic circuit, both as part of a common integrated semiconductor circuit;

providing the integrated semiconductor circuit as a built outside test module remotely from a conventional test unit;

forming a multiplicity of different signal patterns in the addressable memory;

storing the signal patterns in advance in the memory at an address peculiar to the respective signal pattern;

also storing under each address of each signal pattern in the memory in advance a definition in the form of a branch address determining a read-out order of the stored signal patterns and assigning a memory position for a signal pattern to be read out next; and

reading out from the memory and outputting the signal patterns in response to corresponding addressing as a function of the respective current address and of a control signal to be fed in from the control logic circuit, when the control signal is not fed in, in a sequence defined by a serial address or a memory sequence thereof, and when the control signal is fed in, in a sequence determined by the respective branch address.

2. The method according to claim 1 , wherein each signal pattern has three bit locations.

3. The method according to claim 1 , which comprises, if the control signal is not activated, continuously outputting a currently addressed signal pattern.

4. The method according to claim 1 , which comprises, if the control signal is not activated, continuously outputting stored signal patterns in an order given by the sequence defined by the serial address or the memory sequence, and, after a last signal pattern has been output, continuing the process with the outputting of a first stored signal pattern.

5. The method according to claim 1 , wherein, if the control signal is activated, the branching to a next signal pattern assigned by the branch address takes place after the outputting of the currently addressed signal pattern has been completed.

6. The method according to claim 1 , wherein the signal patterns are stored and output as a sequence of three-bit signal patterns for bank select signals in test equipment for testing high-speed dynamic semiconductor memory modules.

7. The method according to claim 6 , wherein the dynamic semiconductor memory modules are 256 M SDRAMs with four memory banks.

8. The method according to claim 1 , wherein the addressable memory is configured as a buffer register and a control logic circuit connected to the buffer register is configured for generating addresses for the buffer register.

9. The method according to claim 8 , wherein the control logic circuit and the buffer register are forming a part of an integrated semiconductor circuit for testing the dynamic digital circuits and configured to generate bank select signals and implemented remotely from a conventional test unit.

10. The method according to claim 9 configured for testing SDRAM memory modules.

11. The method according to claim 1 , which comprises, if the control signal is not activated, continuously outputting the multiplicity of signal pattern groups in sequence according to one of serial addressing and memory sequencing and branch address sequencing, and, after a last signal pattern has been output, continuing the process with the outputting of a first signal pattern of a first group.

12. A method for testing dynamic digital circuits by outputting digital electrical signal pattern groups, which comprises:

providing an addressable memory and a control logic circuit, both as part of a common integrated semiconductor circuit;

providing the integrated semiconductor circuit as a built outside test module remotely from a conventional test unit;

forming a multiplicity of different signal pattern groups each containing a multiplicity of different signal patterns in an addressable memory;

storing the signal pattern groups each in advance in the memory at an address peculiar to the respective signal pattern group;

also storing under each address of each signal pattern group in the memory in advance a definition in the form of a branch address determining a read-out order of the stored signal pattern groups and assigning a memory position for a signal pattern group to be read out next; and

reading out from the memory and outputting the signal pattern groups in response to corresponding addressing as a function of the respective current address and of a control signal to be fed in from the control logic circuit, when the control signal is not fed in, in a sequence defined by a serial address or a memory sequence, and, when the control signal is fed in, in a sequence determined by the respective branch address.

13. The method according to claim 12 , which comprises defining each signal pattern group given by an address with the same number of signal patterns.

14. The method according to claim 12 , wherein each signal pattern group given by an address has four signal patterns.

15. The method according to claim 12 , wherein at least some of the signal pattern groups contain a different number of signal patterns.

16. The method according to claim 12 , which comprises, if the control signal is not activated, continuously outputting a signal pattern or a plurality of signal patterns of a currently addressed signal pattern group.

17. The method according to claim 12 , wherein, if the control signal is activated, the branching to the start of the next signal pattern group assigned by the branch address takes place after the outputting of a currently addressed signal pattern group has been completed.

18. The method according to claim 12 , wherein each of the different signal patterns of the signal pattern groups are stored and output as a sequence of three-bit signal patterns for bank select signals in test equipment for testing high-speed dynamic semiconductor memory modules.