Method for testing circuit units to be tested with increased data compression for burn-in
View Patent ↗The invention creates a method for testing circuit units ( 100 ) to be tested, in which test output signals ( 107 a -107 n ) can be combined, where test input signals ( 106 a -106 n ) are input from a test device ( 105 ) into the circuit unit ( 100 ) to be tested via a connecting unit ( 104 ), the circuit unit ( 100 ) to be tested is tested by means of the test input signals ( 106 a -106 n ) in order to obtain corresponding test output signals ( 107 a -107 n ) which indicate an operability of the circuit unit ( 100 ) to be tested, a gate unit ( 101 ) is connected to the connecting unit ( 104 ) by means of a first test mode switching unit ( 102 ) and of a second test mode switching unit ( 103 ), in such a manner that the test output signals ( 107 a -107 n ), after being logically combined in the gate unit ( 101 ), are provided as a combined test output signal ( 109 ) via a single output line ( 110 ), and the combined test output signal ( 109 ) is output to the test device ( 105 ).
1. A method for testing circuit unit to be tested, in which test output signals are combined, comprising the following steps:
a) inputting test input signals from a test device into the circuit unit to be tested via a connecting unit;
b) testing the circuit unit to be tested by means of the test input signals in order to generate corresponding test output signals which indicate an operability of the circuit unit to be tested;
c) connecting a gate unit to the connecting unit by means of a first test mode switching unit and of a second test mode switching unit, in such a manner that the test output signals, after being logically combined in the gate unit, are provided as a combined test output signal via a single output line; and
d) outputting the combined test output signal to the test device.
2. The method as claimed in claim 1 , wherein the test output signals are switched through the gate unit by means of the first test mode switching unit and the second test mode switching unit when a test mode is activated by the test device.
3. The method as claimed in claim 1 , wherein the first test mode switching unit and the second test mode switching unit exhibit a combination of functions in such a manner that an alternate switching-through of a test line and of gate unit input lines is provided.
4. A device for testing circuit unit to be tested, comprising:
a) a connecting unit for inputting test input signals from a test device into the circuit unit to be tested;
b) a gate unit for logically combining test output signals caused by the test input signals in the circuit unit to be tested;
c) a first test mode switching unit; and
d) a second test mode switching unit which exhibits a combination of functions with the first test mode switching unit, the gate unit being connectable to the connecting unit by means of the first test mode switching unit and the second test mode switching unit, in such a manner that the test output signals, after being logically combined in the gate unit, are available as a combined test output signal via a single output line.
5. The device as claimed in claim 4 , wherein the gate unit is constructed as an OR gate when the test output signals indicate with a logical zero a faultless state and with a logical one a faulty state.
6. The device as claimed in claim 4 , wherein the gate unit is constructed as an AND gate when the test output signals indicate with a logical one a faultless state and with a logical zero a faulty state.
7. The device as claimed in claim 4 , wherein the gate unit is constructed with bipolar transistors.
8. The device as claimed in claim 4 , wherein the gate unit is constructed with field-effect transistors.
9. The device as claimed in claim 4 , wherein the first test mode switching unit and the second test mode switching unit are constructed with bipolar transistors.
10. The device as claimed in claim 4 , wherein the first test mode switching unit and the second test mode switching unit are constructed with field-effect transistors.
11. The device as claimed in claim 4 , wherein a number of test lines corresponds to a number of gate input lines.
12. The device as claimed in claim 4 , wherein the connecting unit is constructed in such a manner that test input signals can be applied to all test lines and a combined test output signal can be picked up via one of the test lines.