IP Library Granted Patent US 7,396,749
Granted Patent B2
US 7,396,749 · App. 10/519,741 · Granted Jul 8, 2008

Method for contacting parts of a component integrated into a semiconductor substrate

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Quick Facts
Patent No.
US 7,396,749
App. No.
10/519,741
Granted
Jul 8, 2008
Kind
B2
Abstract

The invention relates to a method for contacting parts of a component integrated into a semiconductor substrate ( 1 ). According to the inventive method, a first contact hole is produced in an insulating layer ( 2 ), said contact hole being then filled with contact material ( 16 ) and connected to a line. The aim of the invention is to minimise the processes required for contacting parts of a component integrated into a semiconductor substrate. To this end, the hard mask ( 3 ) used to produce the contact hole is also used to structure the line.

Claims (22)

1. A method of forming electrically connected contacting parts of a component integrated into a semiconductor substrate, the method comprising:

providing a hard mask patterned over an insulating layer to define a contact hole; forming said contact hole in said insulating layer; filling the contact hole with an ARC layer that also overlies said patterned hard mask and the insulating layer; depositing and patterning a photoresist layer on said ARC layer; removing portions of the ARC layer and portions of the hard mask not covered by the photoresist layer to repattern said hard mask to define a conductive line trench; removing portions of the insulating layer to form said conductive line trench; removing the ARC layer from the contact hole; and filling the contact hole and said conductive line trench with contact material so that the filled contact hole and the conductive line trench are electrically connected.

2. The method of claim 1 wherein said hard mask is made from polycrystalline silicon.

3. The method of claim 1 further comprising patterning said hard mask by means of a dry etching process.

4. The method of claim 3 wherein said dry etching process comprises using at least one of the group SF 6 , HBr and He/O 2 .

5. The method of claim 1 further comprising depositing a liner on a surface of said contact hole and conductive line trench prior to said step of filling with contact material.

6. The method of claim 5 wherein said liner is selected from the group consisting of Ti and TiN.

7. The method of claim 1 wherein said step of filling the contact hole and the conductive line trench comprises filling with tungsten.

8. A method of forming a contact hole and a conductor trench connecting to said contact hole in an insulating layer using a common hard mask, the method comprising:

providing said insulating layer;

providing said hard mask, said hard mask patterned to form said contact hole;

etching said contact hole in said insulating layer;

covering said insulating layer with an ARC layer to fill said contact hole;

re-patterning said hard mask subsequent to said step of covering said insulating layer with said ARC layer to define said conductor trench connected to said contact hole;

etching said conductor trench in said insulating layer according to said re-pattered hard mask; and

filling said contact hole and said conductor trench with a conductive material such that said conductive material in said conductor trench and said contact hole are electrically connected.

9. The method of claim 8 wherein said hard mask is made from polycrystalline silicon.

10. The method of claim 8 wherein said step of re-patterning said hard mask comprises etching said hard mask by means of a dry etching process.

11. The method of claim 10 wherein said dry etching process comprises using at least one of the group SF 6 , HBr and He/O 2 .

12. The method of claim 8 further comprising a step of depositing a liner on a surface of said contact hole and conductor trench prior to said step of filling.

13. The method of claim 8 wherein said step of filling said contact hole and conductor trench with conductive material comprises filling said contact hole and conductor trench with tungsten.

14. The method of claim 12 wherein said liner is selected from the group consisting of Ti and TiN.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2020
From: POLARIS INNOVATIONS LIMITED
To: CHANGXIN MEMORY TECHNOLOGIES, INC
Reel/Frame 051917/0581 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT 7105729 PREVIOUSLY RECORDED AT REEL: 036827 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 26, 2017
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 043336/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036827/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2005
From: DITTMAR, LUDWIG; GUSTIN, WOLFGANG; STEGEMANN, MAIK
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016997/0035 →