Patent Assignment
Reel/Frame 036396/0646
Assignment of Assignor's Interest
Recorded: 2015-08-19
Pages: 11
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(135)
Method for singling semiconductor components and semiconductor component singling device
Patent:
6,364,751 →
Application:
09/546,421 →
Semiconductor memory with a plurality of memory banks
Patent:
6,226,219 →
Application:
09/549,275 →
Circuit Configuration for Thr Burn-in Test of a Semiconductor Module
Patent:
6,581,171 →
Application:
09/550,212 →
Configuration for Carrying Out Burn-in Processing Operations of Semiconductor Devices at Wafer Level
Patent:
6,535,009 →
Application:
09/553,126 →
Semiconductor memory configuration with a built-in-self-test
Patent:
6,295,237 →
Application:
09/553,127 →
Semiconductor memory of the random access type with a bus system organized in two planes
Patent:
6,295,236 →
Application:
09/553,128 →
Bottom Resist
Patent:
6,514,663 →
Application:
09/560,542 →
Circuit configuration for programming an electrically programmable element
Patent:
6,344,757 →
Application:
09/566,067 →
Method for cob mounting of electronic chip on a circuit board
Patent:
6,312,962 →
Application:
09/566,936 →
Circuit configuration for monitoring states of a memory device
Patent:
6,288,939 →
Application:
09/568,941 →
Circuit configuration for programming an electrically programmable element
Patent:
6,366,518 →
Application:
09/571,486 →
Method of Testing a Semiconductor Memory, and Semiconductor Memory with a Test Device
Patent:
6,539,505 →
Application:
09/574,702 →
Wafer Processing System
Patent:
6,542,837 →
Application:
09/574,823 →
Integrated Memory Having a Redundancy Function
Patent:
6,484,277 →
Application:
09/575,056 →
Semiconductor Module with a Number of Semiconductor Chips and a Conductive Connection Between the Semiconductor Chips by Flexible Tapes
Patent:
6,507,106 →
Application:
09/577,060 →
Semiconductor Module Having Interconnected Semiconductor Chips Disposed One Above the Other
Patent:
6,646,333 →
Application:
09/577,065 →
Circuit Configuration for Repairing a Semiconductor Memory
Patent:
6,601,194 →
Application:
09/580,034 →
Integrated memory having redundant units of memory cells, and test method for the redundant units
Patent:
6,285,605 →
Application:
09/580,982 →
Method for Bonding Conductors, in Particular Beam Leads
Patent:
6,430,809 →
Application:
09/580,983 →
Chip Carrier Having Ventilation Channels
Patent:
6,486,538 →
Application:
09/580,984 →
Integrated memory with a block writing function and global amplifiers requiring less space
Patent:
6,351,419 →
Application:
09/580,986 →
Electronic circuit having a flexible intermediate layer between electronic components and a heat sink
Patent:
6,377,460 →
Application:
09/583,131 →
Integrated memory having 2-transistor/2-capacitor memory cells
Patent:
6,307,771 →
Application:
09/584,329 →
Transport Device for Electronic Components with an Anticontamination Coating
Patent:
6,497,932 →
Application:
09/597,348 →
Integrated circuit having a command decoder
Patent:
6,404,699 →
Application:
09/603,742 →
Integrated Memory
Patent:
6,437,410 →
Application:
09/603,749 →
An Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated
Patent:
6,385,123 →
Application:
09/606,589 →
Integrated circuit for generating a phase-shifted output clock signal from a clock signal
Patent:
6,285,228 →
Application:
09/606,594 →
Integrated circuit with a phase locked loop
Patent:
6,351,167 →
Application:
09/608,563 →
Synchronous integrated memory
Patent:
6,275,445 →
Application:
09/617,649 →
Integrated memory
Patent:
6,272,035 →
Application:
09/618,124 →
Integrated Semiconductor Circuit with an Increased Operating Voltage
Patent:
6,441,677 →
Application:
09/621,430 →
Synchronous Integrated Memory
Patent:
6,928,025 →
Application:
09/621,905 →
Arrangement and Method for Testing a Multiplicity of Semiconductor Chips at the Wafer Level
Patent:
6,549,028 →
Application:
09/630,972 →
Contact Connection of Metal Interconnects of an Integrated Semiconductor Chip
Patent:
6,515,374 →
Application:
09/633,704 →
Method for fabricating a microelectronic structure
Patent:
6,368,940 →
Application:
09/642,325 →
Configuration and Method for Producing Test Signals for Testing a Multiplicity of Semiconductor Chips
Patent:
6,618,836 →
Application:
09/642,326 →
Method of Fabricating Integrated Circuits Having Transistors and Further Semiconductor Elements
Patent:
6,436,750 →
Application:
09/645,765 →
Epitaxy layer and method for its production
Patent:
6,326,262 →
Application:
09/651,492 →
Method for Producing an Electrical Connection Between the Front and Rear Sides of Semiconductor Chips
Patent:
6,406,937 →
Application:
09/658,713 →
Dram Cell Arrangement and Method for Fabricating It
Patent:
6,349,052 →
Application:
09/660,453 →
Integrated memory with two burst operation types
Patent:
6,310,824 →
Application:
09/662,255 →
Integrated memory having memory cells and reference cells
Patent:
6,310,812 →
Application:
09/662,256 →
Integrated memory with at least two plate segments
Patent:
6,314,018 →
Application:
09/662,257 →
Input Buffer of an Integrated Semiconductor Circuit
Patent:
6,480,039 →
Application:
09/662,957 →
Patterning of Contact Areas in Multilayer Metalization Configurations of Semiconductor Components
Patent:
6,559,547 →
Application:
09/663,569 →
Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines
Patent:
6,310,793 →
Application:
09/663,583 →
Deposition of Various Base Layers for Selective Layer Growth in Semiconductor Production
Patent:
6,380,074 →
Application:
09/666,526 →
Configuration for Voltage Buffering in a Dynamic Memory Using Cmos Technology
Patent:
6,469,355 →
Application:
09/671,452 →
Configuration for Reducing the Number of Measuring Pads on a Semiconductor Chip
Patent:
6,433,617 →
Application:
09/672,625 →
Trimming Mask with Semitransparent Phase-Shifting Regions
Patent:
6,466,373 →
Application:
09/677,321 →
Integrated dynamic semiconductor memory having redundant units of memory cells, and a method for self-repair
Patent:
6,304,499 →
Application:
09/677,357 →
Integrated Circuit Configuration with at Least One Capacitor and Method for Producing the Same
Patent:
6,525,363 →
Application:
09/677,433 →
Configuration and Method for Connecting Conductor Tracks
Patent:
6,492,729 →
Application:
09/685,659 →
Dram cell circuit
Patent:
6,362,502 →
Application:
09/692,118 →
controlling transistor threshold potentials using substrate potentials
Patent:
6,353,357 →
Application:
09/693,769 →
Voltage generator with superimposed reference voltage and deactivation signal
Patent:
6,285,176 →
Application:
09/693,778 →
Integrated memory
Patent:
6,295,219 →
Application:
09/699,982 →
Integrated memory having cells of the two-transistor/two-capacitor type
Patent:
6,292,386 →
Application:
09/699,983 →
Needle-Card Adjusting Device for Planarizing Needle Sets on a Needle Card
Patent:
6,674,627 →
Application:
09/705,599 →
Memory device
Patent:
6,314,031 →
Application:
09/711,864 →
Method for carrying out auto refresh sequences on a DRAM
Patent:
6,363,024 →
Application:
09/716,871 →
Standby Voltage Controller and Voltage Divider in a Configuration for Supplying Voltages to an Electronic Circuit
Patent:
6,489,759 →
Application:
09/716,901 →
Integrated Memory Having Memory Cells and Reference Cells
Patent:
6,438,053 →
Application:
09/718,937 →
Method of Testing Memory Cells with a Hysteresis Curve
Patent:
6,456,098 →
Application:
09/722,118 →
Substrate with at Least Two Metal Structures Deposited Thereon, and Method for Fabricating the Same
Method for Fabricating a Field-Effect Transistor Having an Anti-Punch-Through Implantation Region
Lithography Method and Lithography Mask
Method for producing a metal layer with a given thickness
Method for Manufacturing an Integrated Circuit Having a Particular Functionality Required by a User of the Circuit and Having First Structure to Produce the Particular Functionality and Second Structures
Methods for Producing a Structured Metal Layer
Integrated Dynamic Semiconductor Memory with Time Controlled Read Access
Method of Producing a Semiconductor Device Comprising a Cleaning Process for Removing Silicon-Containing Material
Configuration for Trimming Reference Voltages in Semiconductor Chips, in Particular Semiconductor Memories
Bus System
Semiconductor memory of the dynamic random access type (DRAM) and method for actuating a memory cell
Configuration for Measurement of Internal Voltages of an Integrated Semiconductor Apparatus
Dielectric Filling of Electrical Wiring Planes
Integrated Memory Having Memory Cells and Reference Cells, and Corresponding Operating Method
Plant for Producing Semiconductor Products
Operating Method for an Integrated Memory Having Writeable Memory Cells and Corresponding Integrated Memory
Installation for Processing Wafers
Plant for Producing Semiconductor Products
Device for Evaluating Cell Resistances in a Magnetoresistive Memory
Memory Cell Configuration with Capacitor on Opposite Surface of Substrate and Method for Fabrication the Same
Device for Evaluating Cell Resistances in a Magnetoresistive Memory
Method for Processing Wafer by Applying Layer to Protect the Backside During a Tempering Step and Removing Contaminated Portions of the Layer
Semiconductor Storage Component with Storage Cells, Logic Areas and Filling Structures
Patent:
6,670,662 →
Application:
09/980,386 →
Soi Dram Without Floating Body Effect
Patent:
6,599,797 →
Application:
09/980,811 →
Method for Depositing a Two-Layer Diffusion Barrier
Double Gate Mosfet Transistor and Method for the Production Thereof
Charge Pump with Charge Equalization for Improved Efficiency
Computer-Assisted Method for the Parallel Calculation of the Operating Point of Electric Circuits
Patent:
7,024,648 →
Application:
10/009,979 →
Capacitor for Semiconductor Configuration and Method for Fabricating a Dielectric Layer Therefor
Method for Fabricating a Semiconductor Memory Component
Configuration of Fuses in Semiconductor Structures with Cu Metallization
Fuse for a Semiconductor Configuration and Method for Its Production
Electronic Component with Flexible Bonding Pads and Method of Producing Such a Component
Multichip Module for Loc Mounting and Method for Producing the Multichip Module
Electronic Configuration with Flexible Bonding Pads
Mos Transistor and Dram Cell Configuration
Method for Fabricating a Patterned Layer
Testing Device for Testing a Memory
Tsop Memory Chip Housing Configuration
Method for Producing a Semiconductor Memory Element
Patent:
6,716,643 →
Application:
10/048,192 →
Nonvolatile Semiconductor Memory Cell and Method for Fabricating the Memory Cell
Electronic Circuit for a Method for Storing Information, Said Circuit Comprising Feroelectric Flipflops
Patent:
6,833,731 →
Application:
10/070,025 →
Etching Process for a Two-Layer Metallization
Method for Patterning an Organic Antireflection Layer
Process for Etching Bismuth-Containing Oxide Films
Method of Transferring a Pattern of High Structure Density by Multiple Exposure of Less Dense Partial Patterns
Trench with Buried Plate and Method for Its Production
Stacked via with Specially Designed Landing Pad for Integrated Semiconductor Structures
Memory with Trench Capacitor and Selection Transistor and Method for Fabricating It
Memory Device
Patent:
6,624,461 →
Application:
10/089,910 →
Method of Fabricating an Integrated Circuit Configuration with at Least One Capacitor
Mos Transistor and Method for Producing the Transistor
Trench Capacitor with Capacitor Electrodes
Package for a Semiconductor Chip
Patent:
6,724,076 →
Application:
10/111,294 →
Integrated Circuit Configuration Having at Least Two Capacitors and Method for Manufacturing an Integrated Circuit Configuration
Configuration for Evaluating a Signal Which Is Read from a Ferroelectric Storage Capacitor
Method of Producing a Capacitor Electrode with a Barrier Structure
Dram Cell Structure with Tunnel Barrier
Patent:
7,180,115 →
Application:
10/130,441 →
Plant for Processing Wafers
Installation for Processing Wafers
Casing Configuration of a Semicoductor Component
Memory Device
Method for Fabricating an Insulation Collar in a Trench Capacitor
Metallizing Method for Dielectrics
Alternating Phase Mask
Method for Fabricating a Hard Mask
Method for Producing Resist Structures
Data Memory
Integrated Semiconductor Circuit with an Increased Operating Voltage
Method of Producing an Electronic Component with Flexible Bonding Pads
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.