Encasing arrangement for a semiconductor component
View Patent ↗A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.
1. A semiconductor component package configuration, comprising:
a semiconductor chip having wiring terminals;
a printed circuit board having said semiconductor component mounted thereon;
a substrate configured between said semiconductor chip and said printed circuit board, said substrate for routing said wiring terminals of said semiconductor chip to said printed circuit board;
solder joints connecting said substrate to said printed circuit board;
a filler configured between said semiconductor chip and said substrate, said filler for mechanically isolating said semiconductor chip and said soldered joints;
a metal layer applied to said substrate, said metal layer being connected to at least one of said solder joints; and
at least one molded element of heat-dissipating material applied to said metal layer, said molded element connected in a heat-conducting manner to said metal layer, said molded element not directly contacting said semiconductor chip.
2. The configuration according to claim 1 , wherein:
said molded element is configured between said substrate and said semiconductor chip and protrudes into said filler; and
said molded element is at a distance of about 10–20 μm from said semiconductor chip.
3. The configuration according to claim 2 , wherein: said molded element is formed as a cylinder.
4. The configuration according to claim 1 , wherein: said molded element is formed from metal.
5. The configuration according to claim 4 , wherein: said molded element has been electrodeposited onto said metal layer.
6. The configuration according to claim 4 , wherein: said molded element has been applied to said metal layer by a mask etching process.
7. The configuration according to claim 1 , wherein:
said substrate has a side facing said semiconductor chip;
said semiconductor chip has a side; and
said molded element is configured on said side of said substrate facing said semiconductor chip and to said side of said semiconductor chip.
8. The configuration according to claim 7 , wherein:
said molded element is formed as an electrically conductive, metallic frame surrounding said semiconductor chip; and
said molded element is connected to ground potential.
9. The configuration according to claim 7 , comprising: a heat-conducting adhesive connecting said molded element to said metal layer.
10. The configuration according to claim 7 , wherein: said molded element is bonded to said metal layer.
11. The configuration according to claim 7 , comprising: an additional, electrically non-conducting, thermally conductive connection configured between said semiconductor chip and said molded element.