Double gate MOSFET transistor and method for the production thereof
View Patent ↗A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.
1. A method for fabricating a double gate MOSFET, which comprises the steps in the following sequence:
producing gates aligned accurately with one another by;
providing a substrate structure having a silicon substrate layer, a first insulation layer disposed on the silicon substrate layer, a first separation layer disposed on the first insulation layer, and a semiconductor layer disposed on the first separation layer;
patterning the semiconductor layer resulting in a semiconductor layer structure provided as a channel of the double gate MOSFET;
depositing a second separation layer on the semiconductor layer structure and the first separation layer;
completely embedding the semiconductor layer structure in the first and second separation layers by patterning the first and second separation layers;
depositing a second insulation layer on a structure formed of the first and second separation layer;
vertically etching two depressions disposed along one direction, the two depressions dimensioned such that the semiconductor layer structure is situated completely between them, during the etching of the two depressions, the second insulation layer, the first and second separation layers and, in each case on both sides, an edge section of the semiconductor layer structure being etched through completely in each case;
filling the depressions with an electrically conductive material;
forming a contact hole in the second insulation layer;
removing a region of the separation layers extending from the contact hole to the semiconductor layer structure and in which region the semiconductor layer structure is embedded in the separation layers by etching the region of the separation layers through the contact hole;
applying third insulation layers on inner walls of the region of removed separation layers and on surfaces of the semiconductor layer structure; and
introducing a further electrically conductive material into the region of the removed separation layers.
2. The method according to claim 1 , which comprises forming the substrate structure by applying the first insulation layer, the first separation layer, and the semiconductor layer one after another.
3. The method according to claim 2 , which comprises recrystallizing the semiconductor layer after being applied by being irradiated with a laser beam.
4. The method according to claim 1 , which comprises forming the substrate structure by the steps of:
providing the silicon substrate functioning as a first semiconductor substrate;
applying the first insulation layer on the first semiconductor substrate;
providing a second semiconductor substrate;
applying the first separation layer on the second semiconductor substrate;
connecting the first and second semiconductor substrates to one another using a wafer bonding process between the insulation layer and the first separation layer; and
reducing a thickness of the second semiconductor substrate resulting in the semiconductor layer.
5. The method according to claim 1 , which comprises forming the first and second separation layers from silicon nitride.
6. The method according to claim 1 , which comprises planarizing the second insulation layer after being deposited.
7. The method according to claim 1 , which comprises carrying out the step of selectively removing the first and second separation layers through the contact hole made in the second insulation layer.
8. The method according to claim 1 , which comprises forming the electrically conductive material from a material selected from the group consisting of doped polycrystalline silicon, metal and suicide.
9. The method according to claim 8 , which comprises forming the doped polycrystalline silicon by chemical vapor phase deposition and a doping is performed during the deposition.
10. The method according to claim 1 , which comprises selectively removing the first and second separation layers by wet-chemical etching.
11. The method according to claim 1 , which comprises applying the third insulation layers using a thermal oxidation process.
12. The method according to claim 11 , which comprises producing a relatively thin oxide layer on
the surface of the semiconductor layer structure and producing a relatively thick oxide layer on the inner walls of the region of the removed separation layers.
13. The method according to claim 1 , which comprises forming the further electrically conductive material from a material selected from the group consisting of doped polycrystalline silicon, metal and silicide.
14. The method according to claim 13 , which comprises forming the doped polycrystalline silicon by chemical vapor phase deposition and a doping is performed during the chemical vapor phase deposition.
15. The method according to claim 1 , which comprises applying an oxide layer as the first insulation layer.
16. The method according to claim 1 , which comprises applying a silicon layer as the semiconductor layer.
17. The method according to claim 1 , which comprises depositing an oxide layer as the second insulation layer.
18. The method according to claim 1 , which comprises applying oxide layers as the third insulation layers.
19. The method according to claim 9 , which comprises using arsenic atoms in the doping process.
20. The method according to claim 14 , which comprises using phosphorous atoms in the doping process.