DRAM cell structure with tunnel barrier
View Patent ↗The invention relates to a transistor that is provided with a first source/drain area (S/D 1 ), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2 ) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D 1 ). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D 1 ) are arranged in the insulating area. The second source/drain area (S/D 2 ) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.
1. A circuit, comprising:
at least one vertical transistor having a first source/drain region, a channel region arranged above the first source/drain region and adjoining the first source/drain region, a second source/drain region, arranged above the channel, a gate dielectric and a gate electrode;
exactly one tunnel barrier layer arranged such that the second source/drain region is separated from the channel region only by the exactly one tunnel barrier layer;
at least one capacitor having a first capacitor electrode arranged below the channel in a manner to be vertically opposite to the second source/drain region and connected to the first source/drain region by means of a conductive structure; and
an insulating structure including the exactly one tunneling barrier layer, a capacitor dielectric and an insulation layer, the insulation layer being arranged above the first electrode in a manner to be vertically between the channel and the first electrode, whereby the insulating structure surrounds a portion of the at least one vertical transistor and the at least one capacitor and defining an insulating region, with at least the first capacitor electrode and the first source/drain region arranged in the insulating region, and at least the second source/drain region and a second capacitor electrode of the capacitor arranged outside the insulating region, the exactly one tunneling barrier layer arranged between the channel region and the second source/drain region, the gate electrode surrounds the channel region in such a way that the tunneling barrier is controllable, and the capacitor dielectric isolates the first capacitor electrode from the second capacitor electrode, and the conductive structure adjoining the side wall of the insulating layer.
2. A circuit according to claim 1 , further comprising the part of the channel region in which the tunneling barrier is not arranged adjoins the tunneling barrier and the first source/drain region.
3. A circuit according to claim 1 , further comprising a DRAM cell arrangement having memory cells, wherein the transistor and the capacitor are part of one of the memory cells.
4. A circuit according to claim 3 , further comprising:
word lines, the word lines being connected to the gate electrodes of the transistor of the memory cells; and
bit lines, the bit lines being connected to the second capacitor electrodes of the capacitors of the memory cells, said bit lines running transversely with respect to the word lines.
5. A circuit according to claim 1 , in which the transistor is configured as a MOS transistor.