Patent Assignment
Reel/Frame 036305/0890
Assignment of Assignor's Interest
Recorded: 2015-08-07
Pages: 11
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(134)
Reduction of Pad Erosion
Patent:
5,907,771 →
Application:
08/940,233 →
Reliable Policide Gate Stack with Reduced Sheet Resistance and Thickness
Patent:
6,376,348 →
Application:
08/940,235 →
Dishing Resistance
Patent:
5,928,959 →
Application:
08/940,808 →
Hard Etch Mask
Patent:
6,020,091 →
Application:
08/940,891 →
Method for Patterning Integrated Circuit Conductors
Patent:
6,071,820 →
Application:
08/940,892 →
Dual Damascene Process for Metal Layers and Organic Intermetal Layers
Patent:
6,066,569 →
Application:
08/940,895 →
Power-On Detection and Enabling Circuit with Very Fast Detection of Power-Off
Patent:
5,942,925 →
Application:
08/940,899 →
Secondary Sense Amplifier with Window Discriminator for Self-Timed Operation
Patent:
5,982,673 →
Application:
08/941,606 →
Gapfill of Semiconductor Structure Using Doped Silicate Glasses
Patent:
6,096,654 →
Application:
08/942,273 →
Semiconductor Memory Having Hierarchical Bit Line Architecture with Non-Uniform Local Bit Lines
Patent:
5,966,315 →
Application:
08/942,275 →
Memory with Word Line Voltage Control
Patent:
6,016,281 →
Application:
08/992,378 →
Memory Array with Reduced Charging Current
Patent:
5,847,986 →
Application:
08/992,379 →
Method for Quantifying Proximity Effects by Measuring Device Performance
Patent:
6,174,741 →
Application:
08/994,273 →
Synchronous Dynamic Random Access Memory Architecture for Sequential Burst Mode
Patent:
6,138,214 →
Application:
08/994,829 →
Dual Damascene with Bond Pads
Patent:
6,033,984 →
Application:
08/997,682 →
Reduced Pad Erosion
Patent:
6,124,206 →
Application:
08/998,856 →
Recessed Shallow Trench Isolation Structure Nitride Liner and Method for Making Same
Patent:
6,960,818 →
Application:
09/000,626 →
Contact Between a Monocrystalline Silicon Region and a Polycrystalline Silicon Structure and Method for Producing Such a Contact
Patent:
6,329,703 →
Application:
09/030,227 →
Method for Producing a Polycrystalline Silicon Structure and Polycrystalline Silicon Layer to Be Produced by the Method
Patent:
6,068,928 →
Application:
09/030,406 →
Recessed Shallow Trench Isolation Structure Nitride Liner and Method for Making Same
Patent:
5,940,717 →
Application:
09/183,246 →
Plastic Compositions for Sheathing a Metal or Semiconductor Body
Patent:
6,365,269 →
Application:
09/197,371 →
An Adjustable Delay Circuit
Patent:
6,097,233 →
Application:
09/228,610 →
Dram Cell Arrangement and Method for Its Production
Patent:
6,147,376 →
Application:
09/228,611 →
Trench Capacitor with Insulation Collar and Method for Producing the Trench Capacitor
Patent:
6,509,599 →
Application:
09/232,081 →
Memory Cell Configuration and Method for Its Fabrication
Patent:
5,994,746 →
Application:
09/232,083 →
Integrated Memory
Patent:
6,216,248 →
Application:
09/243,296 →
Memory Cell Configuration and Corresponding Fabrication Method
Patent:
6,258,658 →
Application:
09/250,362 →
Circuit Arrangement with at Least One Capacitor
Patent:
6,359,296 →
Application:
09/250,516 →
Integrated Memory
Patent:
6,028,815 →
Application:
09/258,940 →
Integrated Circuit and Method for Testing It
Patent:
6,401,224 →
Application:
09/261,100 →
Dram Cell Arrangement
Patent:
6,097,049 →
Application:
09/272,077 →
Mos Transistor in a Single-Transistor Memory Cell Having a Locally Thickened Gate Oxide, and Production Process
Patent:
6,281,079 →
Application:
09/272,968 →
Method for Programming a Rom Cell Arrangement
Patent:
6,044,006 →
Application:
09/273,648 →
Dram Cell Arrangement and Method for Its Production
Patent:
6,044,009 →
Application:
09/274,733 →
Configuration for Indentifying Contact Faults During the Testing of Integrated Circuits
Patent:
6,693,447 →
Application:
09/277,281 →
Method for Fabricating a Stacked Capacitor in a Semiconductor Configuration, and Stacked Capacitor Fabricated by This Method
Patent:
6,403,440 →
Application:
09/285,897 →
Method and Apparatus for the Treatment of Objects, Preferably Wafers
Patent:
6,293,291 →
Application:
09/289,491 →
Configuration for Testing a Plurality of Memory Chips on a Wafer
Patent:
6,529,028 →
Application:
09/302,649 →
Method for Fabricating a Capacitor for a Semiconductor Memory Configuration
Patent:
6,117,790 →
Application:
09/302,655 →
Optimized-Delay Multiplexer
Patent:
6,756,820 →
Application:
09/311,118 →
Circuit Configuration for Producing Complementary Signals
Patent:
6,198,328 →
Application:
09/311,120 →
Manufacturing Method for a Capacitor in an Integrated Storage Circuit
Patent:
6,127,220 →
Application:
09/312,571 →
Manufacturing Method for a Capacitor in an Integrated Memory Circuit
Patent:
6,204,119 →
Application:
09/312,572 →
Method of Holding a Wafer and Testing the Integrated Circuits on the Wafer
Patent:
6,359,457 →
Application:
09/313,422 →
Semiconductor Memory Having Differential Bit Lines
Patent:
6,144,590 →
Application:
09/315,328 →
Process for Producing Metal-Containing Layers
Patent:
6,403,473 →
Application:
09/315,329 →
Fuse-Latch Circuit
Patent:
6,215,351 →
Application:
09/321,174 →
Circuit Configuration for Burn-in Systems for Testing Modules by Using a Board
Patent:
6,292,008 →
Application:
09/322,717 →
Configuration for Crosstalk Attenuation in Word Lines of Dram Circuits
Patent:
6,160,747 →
Application:
09/322,718 →
Bonding Pad Test Configuration
Patent:
6,229,206 →
Application:
09/326,366 →
Integrated Semiconductor Circuit Having Dummy Structures
Patent:
6,294,841 →
Application:
09/327,699 →
Device for the Deposition of Substances
Patent:
6,258,153 →
Application:
09/335,561 →
Dynamic Semiconductor Memory Device and Method for Initializing a Dynamic Semiconductor Memory Device
Patent:
6,175,531 →
Application:
09/343,429 →
Dynamic Semiconductor Memory Device and Method for Intializing a Dynamic Semiconductor Memory Device
Patent:
6,157,589 →
Application:
09/343,431 →
Integrated Memory
Patent:
6,101,141 →
Application:
09/344,922 →
Output Driver of an Integrated Semiconductor Chip
Patent:
6,130,549 →
Application:
09/346,379 →
Configuration and Method for Storing the Test Results Obtained by a Bist Circuit
Patent:
6,557,130 →
Application:
09/352,992 →
Configuration for Testing Chips
Patent:
6,366,110 →
Application:
09/353,612 →
Method of Producing a Stacked Capacitor
Patent:
6,190,964 →
Application:
09/356,402 →
Integrated Circuit with a Voltage Regulator
Patent:
6,133,779 →
Application:
09/356,811 →
Integrated Circuit Having a Self-Test Device
Patent:
6,675,322 →
Application:
09/356,813 →
Configuration for Testing Integrated Components
Patent:
6,278,285 →
Application:
09/356,955 →
Process for Cleaning Cvd Units
Patent:
6,656,376 →
Application:
09/360,944 →
Composite Member Composed of at Least Two Integrated Circuits and Method for the Manufacture of a Composite Member Composed of at Least Two Integrated Circuits
Patent:
6,262,476 →
Application:
09/360,973 →
Integrated Semiconductor Chip with Modular Dummy Structures
Patent:
6,307,263 →
Application:
09/363,263 →
Trench Capacitor with an Insulation Collar and Method for Producing a Trench Capacitor
Patent:
6,828,191 →
Application:
09/363,277 →
Integrated Circuit Having a Self-Test Device and Method for Producing the Integrated Circuit
Patent:
6,415,406 →
Application:
09/368,134 →
Method of Testing Leakage Current at a Contact-Making Point in an Integrated Circuit by Determining a Potential at the Contact-Making Point
Patent:
6,313,656 →
Application:
09/372,307 →
Process for Producing Structured Layers, Process for Producing Components of an Integrated Circuit, and Process for Producing a Memory Configuration
Patent:
6,627,496 →
Application:
09/374,893 →
Combined Precharging and Homogenizing Circuit
Patent:
6,081,469 →
Application:
09/374,894 →
Integrated Semiconductor Chip Having Leads to One or More External Terminals
Patent:
6,376,913 →
Application:
09/374,895 →
Integrated Semiconductor Memory with Control Device for Clock-Synchronous Writing and Reading
Patent:
6,188,638 →
Application:
09/384,701 →
Method for the Fabrication of a Doped Silicon Layer
Patent:
6,197,666 →
Application:
09/390,496 →
Integrated Semiconductor Memory
Patent:
6,125,073 →
Application:
09/391,717 →
Layer Configuration with a Material Layer and a Diffusion Barrier Which Blocks Diffusing Material Components and Process for Producing a Diffusion Barrier
Patent:
6,337,239 →
Application:
09/391,720 →
Electronic Circuit Configuration
Patent:
6,356,120 →
Application:
09/394,196 →
Integrated Circuit with Two Operating States
Patent:
6,229,343 →
Application:
09/395,005 →
Capacitor with High-E Dielectric or Ferroelectric Material Based on the Fin Stack Principle and Production Process Using a Negative Mold
Patent:
6,258,656 →
Application:
09/395,316 →
Integrated Circuit Memory Having a Sense Amplifier Activated Based on Word Line Potentials
Patent:
6,181,624 →
Application:
09/398,695 →
Integrated Circuit
Patent:
6,278,292 →
Application:
09/401,022 →
Method for Determining the Drive Capability of a Driver Circuit of an Integrated Circuit
Patent:
6,320,368 →
Application:
09/401,387 →
Integrated Memory Having a Self-Repair Function
Patent:
6,178,124 →
Application:
09/401,388 →
Burn-In Test Device
Patent:
6,268,718 →
Application:
09/401,390 →
Memory Cell Configuration and Production Process Therefor
Patent:
6,274,453 →
Application:
09/405,916 →
Method for Fabricating a Semiconductor Structure
Patent:
6,245,640 →
Application:
09/407,263 →
Gapfill of Semiconductor Structure Using Doped Silicate Glasses
Patent:
6,048,475 →
Application:
09/407,384 →
Integrated Circuit Having a Contact-Making Point for Selecting an Operating Mode of the Integrated Circuit
Patent:
6,188,273 →
Application:
09/408,476 →
Method for Installing Protective Components in Integrated Circuits That Are Constructed from Standard Cells
Patent:
6,562,664 →
Application:
09/408,477 →
Ferroelectric Memory and Method for Preventing Aging in a Memory Cell
Patent:
6,091,625 →
Application:
09/408,479 →
Integrated Circuit with a Configuration Assembly
Patent:
6,160,732 →
Application:
09/408,677 →
Vertical Field Effect Transistor with Internal Annular Gate and Method of Production
Patent:
6,717,200 →
Application:
09/408,688 →
Method and an Apparatus for Treating Wastewater from a Chemical-Mechanical Polishing Process Used in Chip Fabrication
Patent:
6,506,306 →
Application:
09/428,582 →
Method for Dram Cell Arrangement and Method for Its Production
Patent:
6,184,045 →
Application:
09/541,952 →
Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
Patent:
6,380,616 →
Application:
09/617,652 →
Method for fabricating stacked vias
Patent:
6,277,761 →
Application:
09/621,433 →
Olanzapine-N-oxide compositions and methods
Patent:
6,352,984 →
Application:
09/632,584 →
Optical Structure and Method for Producing the Same
Patent:
6,614,575 →
Application:
09/636,521 →
Method for Fabricating a Memory Cell Having a Mos Transistor
Patent:
6,316,315 →
Application:
09/642,328 →
Modularly Expandable Mult-Layered Semiconductor Component
Patent:
6,630,727 →
Application:
09/655,603 →
Memory cell configuration and method for fabricating it
Patent:
6,365,944 →
Application:
09/668,485 →
Method of Positioning a Component Mounted on a Lead Frame in a Test Socket
Patent:
6,541,311 →
Application:
09/680,736 →
Memory Configuration Having Redundant Memory Locations and Method for Accessing Redundant Memory Locations
Patent:
6,466,493 →
Application:
09/690,298 →
Substrate and Method for Manufacturing the Same
Patent:
6,432,792 →
Application:
09/708,279 →
Integrated Circuit Configuration Having at Least One Transistor and One Capacitor, and Method for Fabricating It
Patent:
6,593,614 →
Application:
09/716,336 →
Storage Capacitor for a Dram
Method for writing and reading a ferroelectric memory
Method for Fabricating Semiconductor Components
Dram Memory Capacitor Having Three-Layer Dielectric, and Method for Its Production
Circuit for Determining the Time Difference Between Edges of a First Digital Signal and of a Second Digital Signal
Integrated Circuit
Memory Cell Configuration in Which an Electrical Resistance of a Memory Element Represents an Information Item and Can Be Influenced by a Magnetic Field, and Method for Fabricating It
Integrated Circuit Having a Self-Test Device for Carrying Out a Self-Test of the Integrated Circuit
Integrated Component, Composite Element Comprising an Integrated Component and a Conductor Structure, Chip Card, and Method of Producing the Integrated Component
Method for Fabricating a Memory Cell
Integrated circuit with electrical connection points that can be severed by the action of enegry
Integrated Memory with Interblock Redundancy
Integrated Circuit Comprising Vertical Transistors, and a Method for the Production Thereof
Patent:
6,750,095 →
Application:
09/787,966 →
Method of Repairing Defective Memory Cells of an Integrated Memory
Microelectronic Memory Cell Structure with a Layer of Tin Having N:Ti
Magnetoresistive Element and Use Thereof as a Memory Element in a Memory Cell Configuration
Digital circuit
Magnetoresistive Element and the Use Thereof as Storage Element in a Storage Cell Array
Patent:
6,577,526 →
Application:
09/806,617 →
Selectively Deactivating a First Control Loop in a Dual Control Loop Circuit During Data Transmission
Integrated memory having a differential sense amplifier
Magnetoresistive memory having elevated interference immunity
Magnetoresistive Memory with a Low Current Density
Decoder Element for Generating an Output Signal Having Three Different Potentials and an Operating Method for the Decoder Element
Apparatus for Treating Wastewater from a Chemical-Mechanical Polishing Process Used in Chip Fabrication
Capacitor with High-Epsilon Dielectric or Ferroelectric Material Based on the Fin Stack Principle
Patent:
6,512,259 →
Application:
09/863,925 →
Mos Transistor in a Single-Transistor Memory Cell Having a Locally Thickened Gate Oxide
Method of Producing an Integrated Circuit Configuration
Method for Fabricating a Memory Cell Configuration
Memory Cell Array and Method for Manfacturing It
Patent:
39,799 →
Application:
10/431,849 →
Methods of Using Adhesion Enhancing Layers and Microelectronic Integrated Modules Including Adhesion Enhancing Layers
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →