Semiconductor memory device
View Patent ↗With a P well region being divided, NMOS transistors N 1 and N 3 are formed in the first P well region, and NMOS transistors N 2 and N 4 in the second P well region. Alternatively, with a N well region being divided, PMOS transistor P 1 is formed in the first N well region, and PMOS transistor P 2 in the second N well region.
1. A semiconductor memory device, comprising:
a first inverter consisting of a first PMOS transistor and a first NMOS transistor;
a second inverter consisting of a second PMOS transistor and a second NMOS transistor, an input terminal thereof being connected with an output terminal of the first inverter and an output terminal thereof being connected with an input terminal of the first inverter;
a third NMOS transistor connected with the output terminal of the first inverter; and
a fourth NMOS transistor connected with the output terminal of the second inverter,
wherein first and second P well regions are formed on opposite adjacent sides of an N well region, the first PMOS transistor and the second PMOS transistor are formed in the N well region in which a P+ diffused region is formed by injecting a P-type impurity, the first NMOS transistor and the third NMOS transistor are formed in the first P well region, and the second NMOS transistor and the fourth NMOS transistor are formed in the second P well region, and wherein a first word line is wired to the third NMOS transistor, and a second word line is wired to the fourth NMOS transistor and wherein a first wiring connecting the output terminal of the first inverter with the input terminal of the second inverter, and a second wiring connecting the input terminal of the first inverter with the output terminal of the second inverter are wired in the same wiring layer, and the first word line and the second word line are placed in the same direction.
2. The semiconductor memory device according to claim 1 , wherein the first PMOS transistor and the second PMOS transistor are formed such that a source and a drain align in a direction orthogonal to the first word line and the second word line.
3. The semiconductor memory device according to claim 1 , wherein the source of the first PMOS transistor and the second PMOS transistor is connected with the power supply potential of a P+ diffused region formed in the N well region.
4. The semiconductor memory device according to claim 1 , wherein the first NMOS transistor and the third NMOS transistor are formed such that the sources and the drains of these transistors align in a direction orthogonal to the first word line.
5. The semiconductor memory device according to claim 1 , wherein the second NMOS transistor and the fourth NMOS transistor are formed such that the sources and the drains of these transistors align in a direction orthogonal to the second word line.
6. The semiconductor memory device according to claim 1 , wherein the first P well region and the second P well region constitute a memory cell, and the second P well region and another P well region constitute another memory cell.
7. The semiconductor memory device according to claim 6 , wherein the source of the first NMOS transistor constituting a memory cell and that of the second NMOS transistor constituting another memory cell are connected with the ground potential of a N+ diffused region formed in a P well region.
8. The semiconductor memory device according to claim 1 , wherein the first P well region, the second P well region, and the N well region are formed in a direction orthogonal to the first word line and the second word line in a strip-of-paper shape.
9. The semiconductor memory device according to claim 1 , wherein a power line or a ground line is wired between a bit line connected with the third NMOS transistor and that connected with the fourth NMOS transistor.
10. A semiconductor memory device, comprising:
a first inverter consisting of a first NMOS transistor and a first PMOS transistor;
a second inverter consisting of a second NMOS transistor and a second PMOS transistor, an input terminal thereof being connected with the output terminal of the first inverter, and an output terminal thereof being connected with an input terminal of the first inverter;
a third NMOS transistor connected with the output terminal of the first inverter; and
a fourth NMOS transistor connected with the output terminal of the second inverter,
wherein first and second N well regions are formed on opposite adjacent sides of a P well region, the first to the fourth NMOS transistors are formed in the P well region in which a successive N+ diffused region is formed by injecting an N-type impurity, the first PMOS transistor is formed in the first N well region, and the second PMOS transistor is formed in the second N well region, and wherein a first word line is wired to the third NMOS transistor and a second word line is wired to the fourth NMOS transistor and wherein a first wiring connecting the output terminal of the first inverter with the input terminal of the second inverter, and a second wiring connecting the input terminal of the first inverter with the output terminal of the second inverter are wired in the same wiring layer, and the first word line and the second word line are placed in the same direction.
11. The semiconductor memory device according to claim 10 , wherein the first to the fourth NMOS transistors are formed such that the sources and the drains of these transistors align in a direction orthogonal to the first word line and the second word line.
12. The semiconductor memory device according to claim 10 , wherein the sources of the first NMOS transistor and the second NMOS transistor are connected with the ground potential of a N+ diffused region formed in the P well region.
13. The semiconductor memory device according to claim 10 , wherein the first N well region and the second N well region constitute a memory cell, and the second N well region and another N well region constitute another memory cell.
14. The semiconductor memory device according to claim 13 , wherein the source of the first PMOS transistor constituting a memory cell and that of the second PMOS transistor constituting another memory cell are connected with the power supply potential of a P+ diffused region formed in the N well region.
15. The semiconductor memory device according to claim 10 , wherein the first N well region, the second N well region, and the P well region are formed in a direction orthogonal to the first word line and the second word line in a strip-of-paper shape.
16. The semiconductor memory device according to claim 10 , wherein a power line or a ground line is wired between a bit line connected with the third NMOS transistor and that connected with the fourth NMOS transistor.