Single data line sensing scheme for TCCT-based memory cells
View Patent ↗A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as V DD . One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
1. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node coupled to the sensing circuit configured to be at a first pre-determined level;
wherein the device for providing bias includes a switchable device to reverse polarity of the device for providing bias.
2. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the line and configured to provide a bias to the bit line;
a reference node coupled to the sensing circuit configured to be at a first pre-determined level;
a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line; and
switchable device to temporally couple the first node to the bit line.
3. The sensing circuit of claim 2 , wherein the switchable device is a MOSFET device.
4. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node coupled to the sensing circuit configured to be at a first pre-determined level;
wherein the first pre-charge device includes a switchable device to couple the bit line to a pre-charge node, where the pre-charge node is at the first pre-determined level.
5. The sensing circuit of claim 4 , wherein the first pre-determined level is a potential equivalent to ground.
6. The sensing circuit of claim 4 , wherein the first pre-determined level is a relatively high potential.
7. The sensing circuit of claim 4 , wherein the switchable device is a MOSFET device.
8. The sensing circuit of claim 1 , wherein the sense amplifier comprises two cross-coupled inverters.
9. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line;
a reference node coupled to the sensing circuit configured to be at a first pre-determined level;
a sensing power switchable device coupled between the sense amplifier and another potential to enable operation of the sense amplifier; and
a second pre-charge device coupled to the sense amplifier and configured to pre-charge the sense amplifier;
wherein the sense amplifier comprises two cross-coupled inverters.
10. The sensing circuit of claim 9 , wherein the second pre-charge device includes a switchable device to couple the sense amplifier to pre-charge node, where the sense amplifier pre-charge node is at a second pre-determined level.
11. The sensing circuit of claim 10 , wherein the switchable device is a MOSFET device.
12. The sensing circuit of claim 10 , wherein the second pre-determined level is a potential equivalent to ground.
13. The sensing circuit of claim 10 , wherein the second pre-determined level is a relatively high potential.
14. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line;
a reference node coupled to the sensing circuit configured to be at a first pre-determined level;
a first node connected to a first input of the sense amplifier, the first node configured to coupled with the bit line;
a second node connected to a second amplifier, the second node configured to couple with the reference node; and
switchable device to temporally couple the second node to the reference node.
15. The sensing circuit of claim 14 , wherein the switchable device is a MOSFET device.
16. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line:
a reference node coupled to the sensing circuit configured to be at a first pre-determined level;
a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line;
a second node connected to second input of the sense amplifier, the second node configured to couple with the reference node; and
first and second switchable devices configured to communicate complementary signals from the first and second nodes, respectively.
17. A sensing circuit including a sense amplifier resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node not coupled to a reference memory cell, the reference node configured to be at a first pre-determined level;
wherein the device for providing bias includes a switchable device to reverse polarity of the device for providing bias.
18. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line;
a reference node not coupled to a reference memory cell, the reference node configured to be at a first pre-determined level;
a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line; and
switchable device to temporally couple the first node to the bit line.
19. The sensing circuit of claim 18 , wherein the switchable device is a MOSFET device.
20. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising;
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node not coupled to a reference memory cell, the reference node configured to be at a first pre-determined level;
wherein the first pre-charge device include a switchable device to couple the bit line to a pre-charge node, where the pre-charge node is at the first pre-determined level.
21. The sensing circuit of claim 20 , wherein the first pre-determined level is a potential equivalent to ground.
22. The sensing circuit of claim 20 , wherein the first pre-determined level is a relatively high potential.
23. The sensing circuit of claim 20 , wherein the switchable device is a MOSFET device.
24. The sensing circuit of claim 17 , wherein the sense amplifier comprises two cross-coupled inverters.
25. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node not coupled to a reference memory cell, the reference node configured to be at a first pre-determined level;
a sensing power switchable device coupled between the sense amplifier and another potential to enable operation of the sense amplifier; and
a second pre-charge device coupled to the sense amplifier and configured to pre-charge the sense amplifier;
wherein the sense amplifier comprises two cross-coupled inverters.
26. The sensing circuit of claim 25 , wherein the second pre-charge device include a switchable device to couple the sense amplifier to pre-charge node, where the sense amplifier pre-charge node is at a second pre-determined level.
27. The sensing circuit of claim 26 , wherein the switchable device is a MOSFET device.
28. The sensing circuit of claim 26 , wherein the second pre-determined level is a potential equivalent to ground.
29. The sensing circuit of claim 26 , wherein the second pre-determined level is a relatively high potential.
30. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node not coupled to a reference memory cell, the reference nod configured to be at a first pre-determined level;
a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line;
a second node connected to a second input of the sense amplifier, the second node configured to couple with the reference node; and
switchable device to temporally couple the second node to the reference node.
31. The sensing circuit of claim 30 , wherein the switchable device is a MOSFET device.
32. A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line; and
a reference node not coupled to a reference memory cell, the reference node configured to be at a first pre-determined level;
a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line;
a second node connected to a second input of the sense amplifier, the second node configured to couple with the reference node; and
first and second switchable devices configured to communicate complementary signals from the and second nodes, respectively.