Semiconductor device manufacturing mask substrate and semiconductor device manufacturing method
View Patent ↗A semiconductor device manufacturing method and a semiconductor device manufacturing mask both of which make it possible to suppress a semiconductor-device global step and simply manufacture a highly-reliable semiconductor device. Square dummy patterns each having one side of, for example, 0.25 μm or less are inserted into an area other than an actual pattern lying within a semiconductor device manufacturing mask to thereby uniformize a pattern density, enable etching processing without changing conditions set for every semiconductor device manufacturing mask and prevent an increase in global step of a post-CMP interlayer insulating film.
1. A semiconductor device manufacturing mask substrate comprising:
a plurality of gate mask patterns formed thereon;
an area high in pattern density;
an area low in pattern density; and
a plurality of pseudo patterns formed on said semiconductor device manufacturing mask substrate corresponding to said area low in pattern density,
wherein said pseudo patterns have a predetermined form and a size less than a line width of a gate wiring pattern.
2. The semiconductor device manufacturing mask substrate according to claim 1 , wherein said pseudo patterns are respectively squares each having one side of 0.25 μm or less.
3. The semiconductor device manufacturing mask substrate according to claim 1 , wherein said pseudo patterns are respectively rectangles each having a short side of 0.25 μm or less.
4. The semiconductor device manufacturing mask substrate according to any of claims 1 , 2 and 3 , wherein said pseudo patterns are disposed in a lattice form.
5. The semiconductor device manufacturing mask substrate according to claim 1 , wherein an interval between respective adjacent pseudo patterns is about the size less than a line width of the gate wiring pattern.
6. The semiconductor device manufacturing mask substrate according to claim 2 , wherein an interval between respective adjacent pseudo patterns is about the size less than a line width of the gate wiring pattern.
7. The semiconductor device manufacturing mask substrate according to claim 3 , wherein an interval between respective adjacent pseudo patterns is about the size less than a line width of the gate wiring pattern.
8. The semiconductor device manufacturing mask substrate according to claim 4 , wherein an interval between respective adjacent pseudo patterns is about the size less than a line width of the gate wiring pattern.