Speeding up variable length code decoding on general purpose processors
View Patent ↗A method for decoding using a general purpose processor, comprising the steps of extracting a bit field from a data stream; extracting one or more properties from the data stream; matching the one or more properties with one or more tags in a content addressable memory; and generating a new address in response to the content addressable memory.
1. A method for decoding using a general purpose processor, comprising the steps of:
(A) extracting a bit field from a data stream;
(B) extracting one or more properties from said data stream;
(C) matching said one or more properties with one or more tags in a content addressable memory; and
(D) generating a new address in response to said content addressable memory.
2. The method according to claim 1 , further comprising the step of:
loading a final value containing an uncoded symbol.
3. The method according to claim 1 , wherein said method provides an increase in speed of variable length decoding of a video stream in general purpose processors.
4. The method according to claim 1 , wherein said method implements a bit-oriented variable length decode process.
5. The method according to claim 1 , wherein said one or more properties comprise a leading one count in a bit field, a leading zero count in a bit field, and a count of the number of ones in a bit field.
6. The method according to claim 1 , wherein said method comprises an entropy coding stage of a streaming video compression process.
7. The method according to claim 1 , wherein said method is implemented with a hardware acceleration structure and associated software instructions.
8. The method according to claim 1 , wherein said method is amenable to high level software programming.
9. The method according to claim 1 , wherein said method is easily adopted to multiple unique existing and future video codec standards.
10. The method according to claim 1 , wherein step (A) comprises a bit field extraction stage.
11. The method according to claim 1 , wherein step (B) comprises a bit field properties stage.
12. The method according to claim 1 , wherein step (C) comprises a tag machine stage.
13. The method according to claim 1 , wherein step (D) comprises an address generation stage.
14. The method according to claim 4 , wherein said bit oriented variable length decode process executes an instruction in less than 5 clock cycles.
15. The method according to claim 3 , wherein said video stream is selected from the group consisting of MPEG, H.26X variants, proprietary schemes from Microsoft, and proprietary schemes from Real Networks.
16. The method according to claim 1 , wherein said general purpose processor is a RISC processor.
17. The method according to claim 1 , wherein said content addressable memory comprises a translation lookaside buffer.