Semiconductor device including a capacitance
View Patent ↗It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate ( 165 ), a buried oxide film ( 166 ) and an SOI layer ( 171 ), an isolating oxide film 167 ( 167 a to 167 c ) is selectively formed in an upper layer portion of the SOI layer ( 171 ) with a part of the SOI layer ( 171 ) remaining as a P − well region ( 169 ). Consequently, an isolation (partial isolation) structure is obtained. An N + diffusion region ( 168 ) is formed in the SOI layer ( 171 ) between the isolating oxide films ( 167 a ) and ( 167 b ) and a P + diffusion region ( 170 ) is formed in the SOI layer ( 171 ) between the isolating oxide films ( 167 b ) and ( 167 c ). Consequently, there is obtained a junction type variable capacitance (C 23 ) having a PN junction surface of the P − well region ( 169 ) provided under the isolating oxide film ( 167 b ) and the N + diffusion region ( 168 ).
1. A semiconductor device comprising:
a fixed capacitance formed in a semiconductor substrate and having a capacitance value fixed; and
a variable capacitance formed in said semiconductor substrate and capable of variably controlling a capacitance value, wherein
said fixed and said variable capacitance, are connected to each other in parallel, wherein
said variable capacitance includes a junction capacitance formed by a PN junction portion,
said semiconductor substrate includes a semiconductor substrate of a first conductivity type, and
said junction capacitance includes;
a first semiconductor region of a second conductivity type provided in an upper layer portion of said semiconductor substrate, said first semiconductor region having a PN junction portion together with a region of the first conductivity type of said semiconductor substrate;
a second semiconductor region of the first conductivity type provided in said upper layer portion of said semiconductor substrate; and
an isolating region provided in said upper layer portion of said semiconductor substrate and serving to isolate said first and second semiconductor regions.
2. The semiconductor device according to claim 1 , wherein said fixed capacitance includes an MIM (Metal Insulator Metal) capacitance.
3. The semiconductor device according to claim 1 , wherein said fixed capacitance includes a PIP (Polysilicon Insulator Polysilicon) capacitance.
4. The semiconductor device according to claim 1 , wherein
said fixed capacitance includes an insulated gate capacitance,
said insulated gate capacitance including:
a gate insulating film for a capacitance selectively formed on said semiconductor substrate;
a gate electrode for a capacitance formed on said gate insulating film for a capacitance and receiving a fixed electric potential; and
extraction electrode regions formed to interpose therebetween a body region for a capacitance which is provided under said gate electrode for a capacitance in a surface of said semiconductor substrate.
5. The semiconductor device according to claim 1 , wherein
said fixed capacitance includes a plurality of partial fixed capacitances having different capacitance values.
6. The semiconductor device according to claim 1 , wherein said semiconductor substrate includes an SOI substrate having a substrate, at least a surface of which is insulative, and an SOI layer provided on said surface of said semiconductor substrate, and
said isolating region includes a partial isolating region constituted by a partial insulating region provided in an upper layer portion of said SOI layer and an isolating semiconductor region of the first conductivity type which is a part of said SOI layer present in a lower layer portion, said isolating semiconductor region having a PN junction portion together with said first semiconductor region.
7. The semiconductor device according to claim 1 , further comprising:
first and second suicide regions formed on surfaces of said first and second semiconductor regions, respectively.
8. The semiconductor device according to claim 1 , wherein
said fixed capacitance includes a fixed capacitance having a greater capacitance value than a maximum capacitance value of said variable capacitance.