Embedded sequence checking
View Patent ↗A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.
1. A circuit comprising:
a control function configured to assert (i) a start signal in response to a first value of a predetermined sequence of values in a program signal matching a particular entry value and (ii) a stop signal in response to a second value of said predetermined sequence of values in said program signal matching a particular exit value; and
a checksum function configured to (i) generate a checksum value from said predetermined sequence of values in said program signal between assertions of said start signal and said stop signal and (ii) generate a result value in response to comparing said checksum value with a particular expected value.
2. The circuit according to claim 1 , further comprising a first processor having a program counter function configured to generate said program signal.
3. The circuit according to claim 2 , wherein said program signal is generated in response to an interrupt signal received by said first processor.
4. The circuit according to claim 2 , further comprising a second processor configured to generate an output signal carrying said result value external to said circuit.
5. The circuit according to claim 4 , wherein said second processor is further configured to access said result value from a register in response to a unique combination of at least two items selected from an address item, a data item, a register index item, and a last access criteria item.
6. The circuit according to claim 1 , wherein said sequence of values comprises a sequence of instructions executable within said circuit.
7. The circuit according to claim 1 , further comprising a state machine function configured to sequence both said control function and said checksum function through a plurality of entry values and a plurality of exit values as part of a self-test.
8. The circuit according to claim 1 , further comprising a one-time programmable memory function configured to store a programmed value, wherein said control function is further configured to determine said particular expected value in response to said programmed value.
9. The circuit according to claim 1 , further comprising a register (i) unreadable from external to said circuit and (ii) configured to store a count value, wherein said control function is further configured to store said checksum value in response to said program signal stepping said count value from said first value.
10. The circuit according to claim 1 , further comprising a register unreadable from external to said circuit, wherein said stop signal is asserted prior to said program signal addressing an instruction causing at least one entry in said register to change.
11. The circuit according to claim 1 , further comprising a self-test function configured to sequence said circuit to generate a plurality of said result values.
12. The circuit according to claim 1 , further comprising an interface in communication with at least one of said control function and said checksum function to exchange information external to said circuit.
13. The circuit according to claim 1 , further comprising a memory configured to store selection information, wherein said control function comprises a first select logic configured to select said particular entry value among a plurality of entry values based on said selection information.
14. The circuit according to claim 13 , wherein said control function further comprises a second select logic configured to select said particular exit value among a plurality of exit values based on said selection information.
15. The circuit according to claim 14 , wherein said control function further comprises a third select logic configured to select said particular expected value among a plurality of expected values based on said selection information.
16. The circuit according to claim 15 , further comprising a plurality of test pads coupleable to said memory to read said selection information.
17. A method of operating a circuit, comprising the steps of:
(A) generating a program signal having a sequence of values, wherein each individual value of said sequence of values comprises multiple bits;
(B) generating a checksum value by summing said individual values at a plurality of cycles during a window of operation; and
(C) generating a result value by comparing said checksum value with an expected value defined within said circuit upon conclusion of said window of operation.
18. The method according to claim 17 , further comprising the step of:
beginning said window of operation in response a first value of said sequence of values in said signal matching an entry value.
19. The method according to claim 18 , further comprising the step of:
ending said window of operation in response to a second value of said sequence of values in said program signal matching an exit value.
20. The method according to claim 19 , further comprising the step of:
replacing a next value in said program signal with said exit value in response to a current value of said sequence of values in said program signal matching said entry value.
21. The method according to claim 17 , further comprising the step of:
storing said checksum value at each of said cycles during said window of operation.
22. The method according to claim 21 , further comprising the step of:
storing said checksum value at least two predetermined number of cycles into said window of operation to isolate a particular cycle of said cycles where said checksum value fails comparison with said expected value.
23. The method according to claim 22 , wherein a first of said at least two predetermined number of cycles is approximately one-half a total number of cycles through said window of operation.
24. The method according to claim 23 , wherein a second of said at least two predetermined number of cycles is approximately one-fourth said total number of cycles.
25. The method according to claim 23 , wherein a second of said at least two predetermined number of cycles is an increment from said first predetermined number of cycles.
26. The method according to claim 17 , further comprising the step of:
saving said checksum value calculated a predetermined number of said cycles into said window of operation.
27. The method according to claim 17 , further comprising the step of:
configuring said circuit into a tamper resistant configuration in response to said result value indicating that said checksum value is different than said expected value.
28. The method according to claim 27 , wherein the step of configuring comprises the sub-step of:
disabling at least one function of said circuit.
29. The method according to claim 27 , wherein the step of configuring comprises the sub-step of:
resetting said circuit to a predetermined security level.
30. The method according to claim 27 , wherein the step of configuring comprises the sub-step of:
holding said circuit in a reset mode.
31. The method according to claim 17 , comprising a storage medium for use in a computer, said storage medium for recording a computer program comprising the steps of claim 17 .
32. A circuit comprising:
means for generating a program signal having a sequence of values, wherein each individual value of said sequence of value comprises multiple bits;
means for generating a checksum value by summing said individual values at a plurality of cycles during a window of operation; and
means for generating a result value by comparing said checksum value with an expected value defined within said circuit upon conclusion of said window of operation.
33. A circuit comprising:
a control function configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to said signal matching an exit value;
a checksum function configured to (i) generate a checksum value for said signal between assertions of said start signal and said stop signal and (ii) generate a result signal in response to comparing said checksum value with an expected value; and
a register function (i) unreadable from external to said circuit and (ii) configured to provide a register value to said control function, wherein said control function is further configured to determine said expected value in response to said register value.
34. A method for embedded sequence checking, comprising the steps of:
(A) asserting a start signal in response to a first value of a predetermined sequence of values in a program signal matching a particular entry value;
(B) asserting a stop signal in response to a second value of said predetermined sequence of values in said program signal matching a particular exit value;
(C) generating a checksum value from said predetermined sequence of values in said program signal between assertions of said start signal and said stop signal; and
(D) generating a result value in response to comparing said checksum value with a particular expected value.