Layout structure for a flip chip semiconductor integrated circuit
View Patent ↗There is disclosed a flip chip semiconductor integrated circuit, which comprises an internal cell, an I/O buffer as an interface between the internal cell and an external unit, a solder ball, a GND or power supply wire, and an I/O buffer unit arranged on a chip. In this case, the components except the I/O buffer unit are formed in a unit and arranged on the chip, and the I/O buffer unit includes a signal solder ball for transferring signals with the external unit, an I/O buffer having a signal terminal connected to the signal solder ball, a first I/O buffer GND wire connected to a GND terminal of the I/O buffer, and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer.
1. A flip chip semiconductor integrated circuit comprising:
an internal cell;
a solder ball;
a GND or power supply wire; and
an I/O buffer unit arranged on a chip, the I/O buffer unit including an I/O buffer as an interface between the internal cell and an external unit;
wherein the internal cell, solder ball and ground or power supply wire are arranged in a unit, and
the I/O buffer unit includes; a signal solder ball formed on the I/O buffer unit for transferring signals with the external unit; an I/O buffer having a signal terminal connected to the signal solder ball; a first I/O buffer GND wire connected to a GND terminal of the I/O buffer; and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer.
2. The flip chip semiconductor integrated circuit according to claim 1 , further comprising an I/O buffer GND unit arranged on the chip, which includes an I/O buffer GND solder ball for supplying a GND potential from the external unit to the I/O buffer, and a second I/O buffer GND wire connected to the I/O buffer GND solder ball, and to the first I/O buffer GND wire of the adjacently arranged I/O buffer unit.
3. The flip chip semiconductor integrated circuit according to claim 1 , further comprising an I/O buffer power supply unit arranged on the chip, which includes an I/O buffer power supply solder ball for supplying a power supply potential from the external unit to the I/O buffer, and a second I/O buffer power supply wire connected to the I/O buffer power supply solder ball, and to the first I/O buffer power supply wire of the adjacently arranged I/O buffer unit.
4. The flip chip semiconductor integrated circuit according to claim 1 , further comprising an internal cell GND unit arranged on the chip, which includes an internal cell GND solder ball for supplying a GND potential from the external unit to the internal cell, and a second internal cell GND wire connected to the internal cell GND solder ball, and to a first internal cell GND wire of another adjacently arranged unit.
5. The flip chip semiconductor integrated circuit according to claim 1 , further comprising an internal cell power supply unit arranged on the chip, which includes an internal cell power supply solder ball for supplying a power supply potential from the external unit to the internal cell, and a second internal cell power supply wire connected to the internal cell power supply solder ball, and to a first internal cell power supply wire of another adjacently arranged unit.
6. The flip chip semiconductor integrated circuit according to claim 1 , further comprising a GND unit having no solder balls arranged on the chip, which includes a third internal cell GND wire connected to a first internal cell GND wire of another adjacently arranged unit.
7. The flip chip semiconductor integrated circuit according to claim 1 , further comprising a power supply unit having no solder balls arranged on the chip, which includes a third internal cell power supply wire connected to a first internal cell power supply wire of another adjacently arranged unit.
8. The flip chip semiconductor integrated circuit according to claim 1 , wherein each unit has a size equal to/smaller than a solder ball pitch.
9. A flip chip semiconductor integrated circuit comprising:
an internal cell;
an I/O buffer as an interface between the internal cell and an external unit;
a solder ball;
a GND or power supply wire; and
an I/O buffer unit arranged on a chip,
wherein the I/O buffer unit includes: a signal solder ball for transferring signals with the external unit; an I/O buffer having a signal terminal connected to the signal solder ball; a first I/O buffer GND wire connected to a GND terminal of the I/O butter and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer, and
wherein die I/O buffer is arranged directly below the signal solder ball, and the signal terminal of the I/O buffer is connected through a through-hole to the signal solder ball.
10. The flip chip semiconductor integrated circuit according to claim 9 , wherein the I/O buffer unit includes a shield wire arranged around to the through-hole, and connected to the first I/O buffer GND wire or the first I/O buffer power supply wire.
11. The flip chip semiconductor integrated circuit according to claim 1 , further comprising a unit arranged on the chip, which has a size larger by an integral multiple than a solder ball pitch, and include, a cell larger in size than the solder ball pitch.
12. The flip chip semiconductor integrated circuit according to claim 1 , wherein the internal cell GND and power supply wires of each unit are arranged at a pitch equal to 1/integer of a solder ball pitch.
13. The flip chip semiconductor integrated circuit according to claim 9 , further comprising an I/O buffer GND unit arranged on the chip, which includes an I/O buffer GND solder ball for supplying a GND potential from the external unit to the I/O buffer, and a second I/O buffer GND wire connected to the I/O buffer GND solder ball, and to the first I/O buffer GND wire of the adjacently arranged I/O buffer unit.
14. The flip chip semiconductor integrated circuit according to 9 , further comprising an I/O buffer power supply unit arranged on the chip, which includes an I/O buffer power supply solder ball for supplying a power supply potential from the external unit to the I/O buffer, and a second I/O buffer power supply wire connected to the I/O buffer power supply solder ball, and to the first I/O buffer power supply wire of the adjacently arranged I/O buffer unit.
15. The flip chip semiconductor integrated circuit according to claim 9 , further comprising an internal cell GND unit arranged on the chip, which includes an internal cell GND solder ball for supplying a GND potential from the external unit to the internal cell, and a second internal cell GND wire connected to the internal cell GND solder ball, and to a first internal cell GND wire of another adjacently arranged unit.
16. The flip chip semiconductor integrated circuit according to claim 9 , further comprising an internal cell power supply unit arranged on the chip, which includes an internal cell power supply solder ball for supplying a power supply potential from the external unit to the internal cell, and a second internal cell power supply wire connected to the internal cell power supply solder ball, and to a first internal cell power supply wire of another adjacently arranged unit.
17. The flip chip semiconductor integrated circuit according to claim 9 , further comprising a GND unit having no solder bells arranged on the chip, which includes a third internal cell GND wire connected to a first internal cell GND wire of another adjacently arranged unit.
18. The flip chip semiconductor integrated circuit according to claim 9 , further comprising a power supply unit having no solder balls arranged on the chip, which includes a third internal cell power supply wire connected to a first internal cell power supply wire of another adjacently arranged unit.
19. The flip chip semiconductor integrated circuit according to claim 9 , wherein each unit has a size equal to/smaller than a solder bell pitch.