Clock synchronized non-volatile memory device
View Patent ↗A nonvolatile memory apparatus which includes a plurality of terminals including a clock terminal, a command terminal and an other terminal, a control circuit, and a plurality of nonvolatile memory cells. The clock and command terminals are capable of correspondingly receiving a clock signal and commands which include read and program commands. In an operation in response to the read command, the control circuit reads data from ones of the nonvolatile memory cells, and outputs data via said the other terminal based on the clock signal and in response to the program command, the control circuit is capable of receiving data via the other terminal based on the clock signal and writes data to ones of the nonvolatile memory cells.
1. A nonvolatile memory apparatus comprising:
a plurality of terminals including a clock terminal, a command terminal and an other terminal;
a control circuit; and
a plurality of nonvolatile memory cells,
wherein said clock terminal is capable of receiving a clock signal,
wherein said command terminal is capable of receiving commands which includes a read command and a program command,
wherein in an operation in response to said read command received from said command terminal, said control circuit is capable of reading data from ones of said nonvolatile memory cells, and outputting data via said other terminal except said command terminal in response to said clock signal, and
wherein in an operation in response to said program command received from said command terminal, said control circuit is capable of receiving data via said other terminal except said command terminal in response to said clock signal and writing data to ones of said nonvolatile memory cells.
2. A nonvolatile memory apparatus according to claim 1 , wherein said commands further include an erase command, and
wherein in an operation in response to said erase command, received from said command terminal, said control circuit erases data stored in ones of said nonvolatile memory cells.
3. A nonvolatile memory apparatus comprising:
a plurality of terminals including a clock terminal, a command terminal and an other terminal;
a control circuit; and
a plurality of nonvolatile memory cells,
wherein said clock terminal is capable of receiving a clock signal,
wherein said command terminal is capable of receiving commands which include a read command and a program command,
wherein in an operation in response to said read command received from said command terminal, said control circuit is capable of reading data from ones of said nonvolatile memory cells, and outputting data via said other terminal except said command terminal in response to said clock signal,
wherein in an operation in response to said program command received from said command terminal, said control circuit is capable of receiving data via said other terminal except said command terminal in response to said clock signal and writing data to ones of said nonvolatile memory cells,
wherein said commands further include an erase command,
wherein in an operation in response to said erase command, received from said command terminal, said control circuit erases data stored in ones of said nonvolatile memory cells,
wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,
wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells to within said threshold voltage range indicating said erase state in said operation in response to said erase command, and
wherein said control circuit controls moving said threshold voltage of one nonvolatile memory cell to within threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells within threshold voltage range indicating said erase state, in said operation in response to said program command.
4. A nonvolatile memory apparatus according to claim 3 , wherein said control comprises a circuit, and
wherein in said operation in response to said read command, said circuit senses a status of data according to a threshold voltage of said nonvolatile memory cell which is within whether said threshold voltage range indicating said erase state or said threshold voltage range indicating said program state.
5. A nonvolatile memory apparatus according to claim 4 , wherein said other terminal is a data terminal,
wherein said data terminal is capable of receiving data in said operation of said program command, and
wherein said data terminal is capable of outputting data in said operation of said read command.
6. A nonvolatile memory apparatus comprising:
a control circuit;
a first terminal;
a second terminal;
a third terminal; and
a plurality of nonvolatile memory cells,
wherein said first terminal is capable of receiving a clock signal,
wherein said second terminal is capable of receiving data synchronous with said clock signal and supplying data synchronous with said clock signal,
wherein said third terminal is capable of receiving a signal for specifying one of a plurality of operations which include an erase operation, a read operation and a program operation,
wherein in said erase operation, said control circuit erases data stored in ones of said nonvolatile memory cells,
wherein in said read operation, said control circuit is capable of reading data from ones of said nonvolatile memory cells and serially outputting data to outside via said second terminal, and
wherein in said program operation, said control circuit serially is capable of receiving data from outside via said second terminal and of writing data to ones of said nonvolatile memory cells.
7. A nonvolatile memory apparatus according to claim 6 , wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,
wherein said control circuit controls moving a threshold voltage of ones of said nonvolatile memory cells within a threshold voltage range indicating said erase state in said erase operation, and
wherein said control circuit controls moving a threshold voltage of ones of said nonvolatile memory cells within one of said plurality threshold voltage ranges according to data in said program operation.
8. A nonvolatile memory apparatus according to claim 7 , wherein said control circuit comprises a circuit, and
wherein in said read operation, said circuit decides status of data according to a threshold voltage of said nonvolatile memory cell which is within whether said threshold voltage range indicating said erase state or said threshold voltage range indicating said program state.
9. A nonvolatile memory apparatus comprising:
a control circuit;
a clock terminal;
a data terminal;
a command terminal; and
a plurality of nonvolatile memory cells,
wherein said clock terminal is capable of receiving a clock signal,
wherein said data terminal is capable of receiving data synchronous with said clock signal and supplying data synchronous with said clock signal,
wherein said command terminal is capable of receiving commands which includes a read operation and a program operation,
wherein in an operation of said read command, said control circuit is capable of reading data from ones of said nonvolatile memory cells and serially outputting data to outside via said data terminal synchronous with said clock signal, and
wherein in an operation of said program command, said control circuit is capable of serially receiving data from outside via said data terminal synchronous with said clock signal and writing data to ones of said nonvolatile memory cells.
10. A nonvolatile memory apparatus according to claim 9 , wherein said commands further includes an erase command, wherein in an operation of said erase command, said control circuit erases data stored in ones of said nonvolatile memory cells.
11. A nonvolatile memory apparatus according to claim 10 , wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
wherein said plurality of threshold voltage ranges includes a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,
wherein said control circuit controls moving a threshold voltages of ones of said nonvolatile memory cells within said threshold voltage range indicating said erase state in said operation to said erase command, and
wherein said control circuit controls moving a threshold voltage of one nonvolatile memory cell to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells within threshold voltage range indicating said erase state, in said operation in response to said program command.
12. A nonvolatile memory apparatus according to claim 11 , wherein said control circuit comprises a circuit, and
wherein in said operation in response to said read command, said circuit senses status of data according to a threshold voltage of said nonvolatile memory cell which is within whether said threshold voltage range indicating said erase state or said threshold voltage range indicating said program state.