Granted Patent B2

US 7,210,063 · App. 10/228,390 · Granted Apr 24, 2007

Abstract

Claims (37)

1. A method of programming a programmable non-volatile device while coupled to a circuit in which said programmable non-volatile device is to be used, said method comprising the steps of:

(A) establishing a connection from an external device to a test interface device of said circuit;

(B) changing control of a bus of said circuit from (i) a processor of said circuit to (ii) said test interface device, said bus directly connecting said test interface device, said programmable non-volatile device and said processor;

(C) communicating a plurality of accesses from said external device to said test interface device; and

(D) generating from said test interface device (i) while in control of said bus, (ii) directly to said programmable non-volatile device and (iii) independent of said processor, a plurality of commands on said bus corresponding to said accesses that program said programmable non-volatile device, wherein prior to step (D) and after step (A), said programmable non-volatile device comprises a non-erasable portion containing no pre-programmed information.

2. The method according to claim 1 , wherein said programmable non-volatile device is permanently coupled to said circuit.

3. The method according to claim 1 , wherein step (D) comprises the sub-step of:

programming an entire programmed content of said programmable non-volatile device with information from said external device.

4. The method according to claim 1 , wherein step (C) comprises the sub-step of:

executing an application program on said external device for issuing said accesses to said test interface device, wherein said application program resides in a storage carrier readable by a storage device of said external circuit.

5. The method according to claim 1 , wherein at least one of said plurality of commands generated by said test interface device is a write command recognizable by said programmable non-volatile device on said bus.

6. The method according to claim 1 , wherein at least one of said plurality of accesses received by said test interface device is a read access.

7. The method according to claim 1 , wherein said programmable non-volatile device comprises a memory.

8. The method according to claim 7 , wherein said programmable non-volatile device is an electrically erasable programmable read-only memory.

9. The method according to claim 8 , wherein said programmable non-volatile device is a FLASH memory.

10. The method according to claim 1 , wherein said test interface device is an EJTAG interface compatible device.

11. The method according to claim 1 , wherein said circuit is a set-top box circuit.

12. The method according to claim 1 , wherein said programmable non-volatile device comprises a programmable logic device.

13. An apparatus comprising:

a circuit having (i) a first processor, (ii) a programmable non-volatile device, (iii) a test interface device and (iv) a bus directly connecting said first processor, said programmable non-volatile device and said test interface device,

wherein said test interface device is configured to (A) change control of said bus from (i) said first processor to (ii) said test interface device and (B) generate (i) while in control of said bus, (ii) directly to said programmable non-volatile device and (iii) independently of said first processor, a plurality of commands on said bus corresponding to a plurality of accesses that program said programmable non-volatile device; and

a programming device (A) external to said circuit, (B) coupleable to said test interface device of said circuit, (C) configured to establish a connection to said test interface device and (D) configured to communicate said accesses to said test interface device, wherein prior to programming said programmable non-volatile device and after establishing said connection, said programmable non-volatile device comprises a non-erasable portion containing no pre-programmed information.

14. The apparatus according to claim 13 , wherein said programming device further comprises a second processor for executing an application program.

15. The apparatus according to claim 13 , wherein said programming device further comprises a second processor for executing an application program to communicate data to said programmable non-volatile device, via said test interface device and said bus, independent of said first processor.

16. The apparatus according to claim 13 , wherein said programmable non-volatile device is programmed for controlling an operation of said circuit.

17. The apparatus according to claim 13 , wherein said programming device is an EJTAG interface compatible device.

18. A machine readable computer program product carrying instructions for controlling a computer to program a programmable non-volatile device while the programmable non-volatile device is coupled in a circuit in which the programmable non-volatile device is to be used, said machine readable computer program product comprising the steps of:

(A) establishing a connection from said computer to a test interface device of said circuit;

(B) activating said test interface device to change control of a bus of said circuit from (i) a processor of said circuit to (ii) said test interface device, said bus directly connecting said test interface device, said programmable non-volatile device and said processor; and

(C) communicating a plurality of accesses from said computer to said test interface device such that said test interface device generates (i) while in control of said bus, (ii) directly to said programmable non-volatile device and (iii) independent of said processor, a plurality of commands on said bus corresponding to said accesses that program said programmable non-volatile device, wherein prior to programming said programmable non-volatile device and after establishing said connection, said programmable non-volatile device comprises a non-erasable portion containing no pre-programmed information.

19. A method of programming a programmable non-volatile device while coupled to a circuit in which said programmable non-volatile device is to be used, said method comprising the steps of:

(A) establishing a connection from an external device to a test interface device of said circuit;

(B) changing control of a bus of said circuit from (i) a processor of said circuit to (ii) said test interface device, said bus directly connecting said test interface device, said programmable non-volatile device and said processor;

(C) communicating a plurality of accesses from said external device to said test interface device by executing an application program on said external device for issuing said accesses to said test interface device, wherein (i) said application program resides in a storage carrier readable by a storage device of said external circuit and (ii) at least one of said plurality of accesses received by said test interface device is a read access;

(D) generating from said test interface device (i) while in control of said bus, (ii) directly to said programmable non-volatile device and (iii) independent of said processor, a plurality of commands on said bus corresponding to said accesses that program said programmable non-volatile device; and

(E) transferring a write confirmation signal from said programmable non-volatile device through both said bus and said test interface device to said external device to confirm a successful write operation in said programmable non-volatile device.

20. The method according to claim 19 , wherein prior to step (D) and after step (A), said programmable non-volatile device comprises a non-erasable portion containing no pre-programmed information.

Assignments (9)