Methods and apparatus for utilizing flash burst mode to improve processor performance
Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.
1. Digital processing apparatus comprising:
a processor including a microcontroller for executing microcontroller instructions, the instructions including memory access instructions, said processor generating a next access signal that indicates if a next memory access by said processor is in sequence with a current memory access, wherein the next access signal is asserted when memory accesses are sequential and is deasserted when memory accesses are non-sequential;
a flash memory having a continued burst mode of operation, said memory having a memory bus for communication with said processor; and
a bus interface unit for controlling access to said memory in response to the memory access instructions, said bus interface unit enabling the continued burst mode of the memory while the next access signal is asserted and inhibiting the continued burst mode of the memory when the next access signal is deasserted to provide a continued burst mode of variable length in response to the next access signal and to avoid reading of unused words, wherein the variable length of the continued burst mode is dynamically controlled in response to the next access signal.
2. Digital processing apparatus as defined in claim 1 , wherein said processor, said memory and said bus interface unit constitute a baseband processor for use in a wireless terminal.
3. Digital processing apparatus as defined in claim 1 , wherein said processor, said memory and said bus interface unit are fabricated on a single substrate.
4. A method for accessing memory in a digital processing system, comprising:
providing a processor including a microcontroller which executes microcontroller instructions including memory access instructions, said processor generating a next access signal that indicates if a next memory access by said processor is in sequence with a current memory access, wherein the next access signal is asserted when memory accesses are sequential and is deasserted when memory accesses are non-sequential;
providing a flash memory having a continued burst mode of operation; and
enabling the continued burst mode of the memory while the next access signal is asserted and inhibiting the continued burst mode of the memory when the next access signal is deasserted to provide a continued burst mode of variable length in response to the next access signal and to avoid reading of unused words, wherein the variable length of the continued burst mode is dynamically controlled in response to the next access signal.
5. A baseband processor for wireless applications comprising:
a microcontroller for executing microcontroller instructions including memory access instructions, said microcontroller generating a next access signal that indicates if a next memory access by said microcontroller is in sequence with a current memory access, wherein the next access signal is asserted when memory accesses are sequential and is deasserted when memory accesses are non-sequential;
a flash memory having a continued burst mode of operation, said flash memory having a memory bus for communication with said microcontroller; and
a bus interface unit for controlling access to said flash memory in response to the memory access instructions, said bus interface unit enabling the continued burst mode of the flash memory while the next access signal is asserted and inhibiting the continued burst mode of the memory when the next access signal is deasserted to provide a continued burst mode of variable length in response to the next access signal and to avoid reading of unused words, wherein the variable length of the continued burst mode is dynamically controlled in response to the next access signal, wherein said microcontroller, said flash memory and said bus interface unit constitute a baseband processor of a wireless terminal.